Halbleitereinheit mit Gate-Stapel

    公开(公告)号:DE112011103249T5

    公开(公告)日:2013-08-14

    申请号:DE112011103249

    申请日:2011-09-22

    Applicant: IBM

    Abstract: Die vorliegende Erfindung betrifft eine Halbleitereinheit, die eine Gate-Stapel-Struktur (1) aufweist, wobei die Gate-Stapel-Struktur (1) aufweist: wenigstens ein Substrat (10), das einen Halbleiter aufweist, der mit n-Typ-Trägern wesentlich dotiert ist; wenigstens eine auf dem Substrat (10) gebildete Passivierungsschicht (12), die Silicium aufweist; und wenigstens eine auf der Passivierungsschicht (12) gebildete Isolatorschicht (13), wobei die Gate-Stapel-Struktur (1) ferner aufweist: wenigstens einen Zwischenschicht-Dotierstoff, der zwischen dem Substrat (10) und der Passivierungsschicht (12) bereitgestellt ist, wobei der Zwischenschicht-Dotierstoff einen n-Typ-Dotierstoff (11) aufweist, der ausgewählt ist, um das Steuern einer Schwellenspannung zu ermöglichen, die an die Gate-Stapel-Struktur (1) anwendbar ist, wenn die Halbleitereinheit in Verwendung steht.

    Waveguide structure
    2.
    发明专利

    公开(公告)号:GB2525427A

    公开(公告)日:2015-10-28

    申请号:GB201407260

    申请日:2014-04-24

    Applicant: IBM

    Abstract: The present invention relates to a waveguide structure (1) comprising: a core (2) comprising a layer of electro-optic dielectric material such as barium titanate (3), a layer of semiconductor material (4) provided below the electro-optic material (3) and a layer of semiconductor material (5) provided above the electro-optic material (3), and electrodes (6, 6, 5 7, 8), that are configurable for voltage application, wherein: the electro-optic dielectric material (3) has a Pockels tensor containing at least one non-vanishing element rij where i≠j, and the electrodes (6, 6, 7, 8) comprise respective sets of electrodes (6, 6, 7, 8) comprising a set of electrodes (6, 6) that are provided substantially in direct contact with the electro-optic dielectric material (3), and a further set of electrodes (7, 8) comprising an electrode (7) provided substantially in direct contact with the semiconductor material (4) below the electro-optic material (3) and an electrode (8) provided substantially in direct contact with the semiconductor material (5) above the electro-optic material (3), wherein the respective sets of electrodes (6, 6, 7, 8) are configurable to apply in the electro-optic material (3), when the waveguide structure (1) is in use, a substantially horizontal electrical field (11) and a substantially vertical electrical field (12) that are orientated substantially perpendicular relative to each other.

    Resistive memory element based on oxygen-doped amorphous carbon

    公开(公告)号:GB2516841A

    公开(公告)日:2015-02-11

    申请号:GB201313718

    申请日:2013-07-31

    Applicant: IBM

    Abstract: A resistive memory element preferably a resistive read only memory element (RRAM), comprising a resistively switchable material 14 coupled to two conductive electrodes 12, 16, wherein the resistively switchable material 14 is an amorphous compound comprising 5 carbon and oxygen, the C:O stoichiometric ratio being a range of 1:0.30 to 1:0.80 and preferably in the range 1:0.4 to 0:0.6. The properties of the switching material are determined by the presence of the sp2 bonds which are conducting and the sp3 bonds which are insulating. Preferably the ratio of C-C sp2 bonds to C-C sp3 bonds in the resistively switching material is less than 0.4 preferably less than 0.2 or 0.1 . The resistively switching material may be doped with silicon, hydrogen of nitrogen and may be of thickness 2nm to 30nm. The electrodes may consist of differing materials in contact with the resistively switching material and made from Tungsten, Platinum, graphite, graphene and aluminium. The resistive memory element may comprise a patterned SiO2 insulating layer over an electrode (12, figure 3) to form a cavity enabling a conformal layer of restively switching material to be formed (14, figure 3). Programming of storage information is achieved by a method of applying a voltage pulse between the conductive electrodes and can be unipolar or bipolar. The fabrication process includes a method whereby reactive sputtering in a chamber comprising a graphite target in the presence of oxygen O2 and Argon Ar gases in a plasma state such that oxygenated amorphous material (a-C:O ) is deposited on the conductive electrode 12 (see figure 4).

    Semiconductor device with a gate stack

    公开(公告)号:GB2497257A

    公开(公告)日:2013-06-05

    申请号:GB201306306

    申请日:2011-09-22

    Applicant: IBM

    Abstract: The present invention relates to a semiconductor device comprising a gate stack structure (1), the gate stack structure (1) comprising: at least a substrate (10) comprising a semiconductor that is substantially doped with n-type carriers; at least a passivation layer (12) comprising silicon formed on the substrate (10), and at least an insulator layer (13) formed on the passivation layer (12), wherein the gate stack structure (1) further comprises: at least an interlayer dopant provided between the substrate (10) and the passivation layer (12), the interlayer dopant comprising an n-type dopant (11) that is selected to facilitate control of a threshold voltage applicable to the gate stack structure (1) when the semiconductor device is in use.

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