公开(公告)号：JP2006148093A

公开(公告)日：2006-06-08

申请号：JP2005319160

申请日：2005-11-02

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： HOLMES STEVEN J ,  MARK C HEIKY ,  FURUKAWA TOSHIHARU ,  DAVID V HOLLACK

IPC: H01L21/027 ,  G03F7/20

CPC classification number: G03F7/70341 ,  G03F7/70925

Abstract: PROBLEM TO BE SOLVED: To remove smearing residue in an immersion lithography system. SOLUTION: The equipment for cleaning a semiconductor substrate comprises a chamber having an upper portion, a sidewall and a bottom opening where the upper portion is transparent to light of selected wavelength, an inlet and an outlet provided in the sidewall of the chamber, a plate extending outward from the bottom edge of the chamber, a set of concentric grooves formed in the bottom face of the plate and centering on the chamber, a means for applying vacuum to first and fourth grooves closest to the bottom opening of the chamber in the set of grooves, a means for supplying inert gas or vapor mixture of inert gas and solvent to a second groove between the first and fourth grooves and a fifth groove on the outside of the fourth groove in the set of grooves, and a means for supplying cleaning fluid to a third groove between the second and fourth grooves in the set of grooves. COPYRIGHT: (C)2006,JPO&NCIPI

Abstract translation: 要解决的问题：去除浸没式光刻系统中的污渍残留物。 解决方案：用于清洁半导体衬底的设备包括具有上部，侧壁和底部开口的室，其中上部对于所选波长的光是透明的，入口和出口设置在室的侧壁中 ，从所述室的底部边缘向外延伸的板，形成在所述板的底面中并且以所述室为中心的一组同心槽，用于对最靠近所述室的底部开口的第一和第四凹槽施加真空的装置 在一组凹槽中，用于将惰性气体或惰性气体和溶剂的惰性气体或蒸汽混合物供应到第一和第四凹槽之间的第二凹槽和该组凹槽中的第四凹槽的外侧上的第五凹槽的装置， 用于将清洁流体供应到所述一组凹槽中的第二和第四凹槽之间的第三凹槽。 版权所有（C）2006，JPO＆NCIPI

公开(公告)号：JP2006148092A

公开(公告)日：2006-06-08

申请号：JP2005319158

申请日：2005-11-02

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： HOLMES STEVEN J ,  FURUKAWA TOSHIHARU ,  MARK C HEIKY ,  CORLISS DANIEL A ,  DAVID V HOLLACK ,  KOBURGER CHARLES W

IPC: H01L21/027 ,  G03F7/20 ,  H01L21/683

CPC classification number: G03F7/707 ,  G03F7/70341 ,  G03F7/70808

Abstract: PROBLEM TO BE SOLVED: To provide a method and equipment in which the possibility of bringing immersion fluid from a clearance or other portion of a chuck onto the surface of a photoresist layer on a wafer is not high. SOLUTION: Equipment for holding a wafer and a method for immersion lithography. The equipment comprises a wafer chuck having a central circular vacuum platen, an outside region, and a circular groove centering on the vacuum platen. Upper surface of the vacuum platen is recessed below the upper surface of the outside region, and the layer surface of the groove is recessed below the upper part of the vacuum platen, one or more suction ports are provided in the lower surface of the groove, and a hollow toroidal bladder capable of expansion or contraction is arranged in the groove. COPYRIGHT: (C)2006,JPO&NCIPI

Abstract translation: 要解决的问题：提供一种方法和设备，其中将来自夹盘的间隙或其他部分的浸没流体的可能性提供到晶片上的光致抗蚀剂层的表面上的可能性不高。

解决方案：用于保持晶片的设备和浸没式光刻方法。 该设备包括具有中心圆形真空压板，外部区域和以真空压板为中心的圆形槽的晶片卡盘。 真空压板的上表面在外部区域的上表面下方凹陷，并且凹槽的表面凹陷在真空压板的上部下方，在凹槽的下表面中设置一个或多个吸入口， 并且在槽中布置能够膨胀或收缩的空心环形囊。 版权所有（C）2006，JPO＆NCIPI

公开(公告)号：JP2000036596A

公开(公告)日：2000-02-02

申请号：JP11771499

申请日：1999-04-26

Applicant: IBM

Inventor： FURUKAWA TOSHIHARU ,  MARK C HEIKY ,  STEPHEN J HOLMES ,  DAVID V HORAK

IPC: H01L29/78 ,  H01L21/223 ,  H01L21/28 ,  H01L21/32 ,  H01L21/336 ,  H01L21/8238 ,  H01L27/092

Abstract: PROBLEM TO BE SOLVED: To form a narrow gate and a shallow expansion part by providing a layer (substrate) including one polysilicon gate and one source/drain region, and by simultaneously doping one gate stack and the source/drain region. SOLUTION: Vapor-phase doping is selectively used, and a polysilicon gate and an S/D region are simultaneously doped. Especially, a gate stack 20 and a well 18 that are not doped are covered with an appropriate diffusion prevention material 40. An S/D region 19 and a polysilicon gate 24 are exposed to n- and p-type gases or a doping source 30 of plasma. The gases can be variously changed corresponding to p and n types. For example, arsine AsH3 is used as arsenic trichloride AsCl3, phosphine PH3, and n-type gas dopant. When a masked laser beam is used, a diffusion prevention material 40 is eliminated, and reaction is repeated for the remaining stack 20 and the S/D region 19 by a type opposite to the doping source being used firstly.

公开(公告)号：JP2006150348A

公开(公告)日：2006-06-15

申请号：JP2005312981

申请日：2005-10-27

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： STEVEN J HOLMES ,  MARK C HEIKY ,  HORAK DAVID V ,  RYAN JAMES G

IPC: B01D39/20 ,  B82B1/00 ,  B82B3/00 ,  C01B31/02

CPC classification number: B01D53/02 ,  B01D2253/102 ,  B01D2253/304 ,  B01J20/20 ,  B01J20/205 ,  B01J20/3242 ,  B82Y30/00 ,  Y10S55/05 ,  Y10S977/742 ,  Y10S977/745 ,  Y10S977/748 ,  Y10S977/75 ,  Y10S977/752

Abstract: PROBLEM TO BE SOLVED: To provide a carbon nanotube filter, a method for using the carbon nanotube filter and a method for forming the carbon nanotube filter. SOLUTION: This method is comprised of (a) a step for preparing a carbon source and a carbon nanaotube catalyst, (b) a step for growing the carbon nanotube by reacting the carbon source with the nanotube catalyst, (c) a step for chemically forming the active carbon nanotube by chemically forming an active layer on the carbon nanotube or by chemically forming a reactive medium on the side wall of the carbon nanotube and (d) a step for arranging the chemically active nanotube in a filter housing. COPYRIGHT: (C)2006,JPO&NCIPI

Abstract translation: 要解决的问题：提供一种碳纳米管过滤器，使用碳纳米管过滤器的方法和形成碳纳米管过滤器的方法。 解决方案：该方法包括（a）制备碳源和碳纳托管催化剂的步骤，（b）通过碳源与纳米管催化剂反应生长碳纳米管的步骤，（c） 通过在碳纳米管上化学形成活性层或通过在碳纳米管的侧壁上化学形成反应性介质来化学形成活性碳纳米管的步骤和（d）将化学活性纳米管排列在过滤器壳体中的步骤。 版权所有（C）2006，JPO＆NCIPI

公开(公告)号：JPH1131797A

公开(公告)日：1999-02-02

申请号：JP15505798

申请日：1998-06-03

Applicant: IBM

Inventor： MARK C HEIKY ,  DAVID V HORAK ,  MANDELMAN JACK A ,  WENDEL P NOBLE

IPC: H01L27/04 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/108

Abstract: PROBLEM TO BE SOLVED: To obtain a built-in strap structure which makes a device transfer gate longer in length by the use of a smaller cell region by a method wherein the inside of a storage trench is connected to the rear of an array transfer device, and the strap is arranged in a region which is used only for isolation. SOLUTION: An empty region inside a shallow trench isolation region 82 for a built-in strap which avoids a deep trench collar is used. The layout of a built-in strap indicated by an arrow 80 is carried out in a shallow trench isolation region 82. A space inside a transfer gate 84 between deep trenches 86 is not affected by the built-in strap. By this setup, a built-in strap structure which gives a longer device transfer gate length by the use of a smaller cell region can be obtained.

公开(公告)号：JP2006210927A

公开(公告)日：2006-08-10

申请号：JP2006018863

申请日：2006-01-27

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： FURUKAWA TOSHIHARU ,  MARK C HEIKY ,  STEVEN J HOLMES ,  DAVID V HOLLACK ,  KOBURGER CHARLES W III

IPC: H01L21/20 ,  H01L21/02 ,  H01L21/336 ,  H01L21/76 ,  H01L21/762 ,  H01L27/12 ,  H01L29/423 ,  H01L29/49 ,  H01L29/78 ,  H01L29/786

CPC classification number: H01L29/0653 ,  B82Y10/00 ,  H01L21/28114 ,  H01L21/3086 ,  H01L21/31144 ,  H01L21/76224 ,  H01L21/76243 ,  H01L21/76267 ,  H01L21/76283 ,  H01L29/0649 ,  H01L29/0657 ,  H01L29/1083 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/66575 ,  H01L29/6659 ,  H01L29/66772 ,  H01L29/7833 ,  H01L29/78654 ,  H01L29/78684

Abstract: PROBLEM TO BE SOLVED: To provide an improved method of forming a filled isolation region of a semiconductor substrate, and to provide a method of forming a semiconductor device, having the filled isolation region and cooling the device and giving body potential control. SOLUTION: A semiconductor structure and a method of forming the semiconductor structure are disclosed. The semiconductor structure includes a nanostructure or is manufactured by using the nanostructure. The method of forming the semiconductor structure includes the steps of generating the nanostructure, by using a nano mask and performing an additional semiconductor processing step by using the nanostructure thus generated. COPYRIGHT: (C)2006,JPO&NCIPI

Abstract translation: 要解决的问题：提供一种形成半导体衬底的填充隔离区域的改进方法，并且提供一种形成半导体器件的方法，其具有填充的隔离区域并冷却器件并给出电位控制。 解决方案：公开了半导体结构和形成半导体结构的方法。 半导体结构包括纳米结构或通过使用纳米结构制造。 形成半导体结构的方法包括以下步骤：通过使用纳米掩模产生纳米结构，并通过使用如此生成的纳米结构进行附加的半导体加工步骤。 版权所有（C）2006，JPO＆NCIPI

公开(公告)号：JP2006060227A

公开(公告)日：2006-03-02

申请号：JP2005238138

申请日：2005-08-19

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： MARK C HEIKY ,  MASTERS MARK E ,  PASTEL LEAH M P ,  VALLETT DAVID P

IPC: H01L21/822 ,  H01L21/8234 ,  H01L27/04 ,  H01L27/088 ,  H01L29/06

CPC classification number: H01L29/0665 ,  B82Y10/00 ,  G01R31/2884 ,  H01L27/088 ,  H01L27/286 ,  H01L29/0673 ,  H01L29/78 ,  H01L51/0048 ,  H01L51/0512 ,  Y10S977/761 ,  Y10S977/762 ,  Y10S977/765

Abstract: PROBLEM TO BE SOLVED: To provide a new structure and a new method for monitoring an operation of an acting integrated circuit in operation. SOLUTION: This invention relates to a method and a structure of an integrated circuit provided with a first transistor and an embeded carbon nanotube field effect transistor (CNT FET) which is adjacent to and smaller than the first transistor. The CNT FET is used for sensing a signal containing any of a temperature signal, a voltage signal, a current signal, an electric field signal and a magnetic field signal from the first transistor. Furthermore, the CNT FET is used for measuring a stress and a distortion in the integrated circuit containing any of a mechanical stress and a mechanical distortion as well as a thermal stress and a thermal distortion. Furthermore, the CNT FET is used for detecting a defective circuit in the integrated circuit. COPYRIGHT: (C)2006,JPO&NCIPI

Abstract translation: 要解决的问题：提供用于监视操作中的动作集成电路的操作的新结构和新方法。 解决方案：本发明涉及一种集成电路的方法和结构，该集成电路设置有与第一晶体管相邻且小于第一晶体管的第一晶体管和嵌入式碳纳米管场效应晶体管（CNT FET）。 CNT FET用于感测包含来自第一晶体管的任何温度信号，电压信号，电流信号，电场信号和磁场信号的信号。 此外，CNT FET用于测量包含任何机械应力和机械变形以及热应力和热变形的集成电路中的应力和变形。 此外，CNT FET用于检测集成电路中的故障电路。 版权所有（C）2006，JPO＆NCIPI

公开(公告)号：JP2005197736A

公开(公告)日：2005-07-21

申请号：JP2005000225

申请日：2005-01-04

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： FURUKAWA TOSHIHARU ,  STEVEN J HOLMES ,  MARK C HEIKY ,  DAVID V HOLLACK ,  KOBURGER CHARLES W III ,  MITCHELL PETER H ,  NESBIT LARRY A

IPC: H01L29/06 ,  H01L21/336 ,  H01L29/78 ,  H01L29/786 ,  H01L51/30

CPC classification number: H01L51/057 ,  B82Y10/00 ,  H01L51/0048

Abstract: PROBLEM TO BE SOLVED: To provide a method for forming a field effect transistor having a channel length controlled favorably by applying a carbon nanotube. SOLUTION: The field effect transistor employs the vertically oriented carbon nanotube as a transistor body, the carbon nanotube being formed by deposition within a vertical aperture, with an optional combination of several parallel nanotubes to produce quantized current drive, and an optional change in a chemical composition of a carbon material at the top or at the bottom to suppress short channel effect. COPYRIGHT: (C)2005,JPO&NCIPI

Abstract translation: 解决的问题：提供一种形成通过施加碳纳米管有利地控制沟道长度的场效应晶体管的方法。 解决方案：场效应晶体管采用垂直取向的碳纳米管作为晶体管体，碳纳米管通过在垂直孔内沉积而形成，并且可选地组合几根平行的纳米管以产生量化电流驱动，并且可选地改变 在顶部或底部的碳材料的化学组成中抑制短沟道效应。 版权所有（C）2005，JPO＆NCIPI

公开(公告)号：JP2004214630A

公开(公告)日：2004-07-29

申请号：JP2003396388

申请日：2003-11-26

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： RICHARD WISE ,  MARK C HEIKY ,  PANDA SIDDHARTHA ,  CHEN BOMY A

IPC: H05H1/46 ,  C23C16/513 ,  H01J37/32 ,  H01L21/00 ,  H01L21/205 ,  H01L21/306 ,  H01L21/3065 ,  H01L21/308

CPC classification number: H01J37/32192 ,  H01J37/32357 ,  H01L21/308

Abstract: PROBLEM TO BE SOLVED: To provide a system for effectively separating the reactivity of a gaseous phase reactant and the chemical reaction of a wafer surface. SOLUTION: A processing system, based on previously loaded plasma, is provided with a preliminary reaction plasma processing chamber, a power source connected to the preliminary reaction plasma processing chamber so as to drive the chamber and a wafer plasma processing chamber connected to the preliminary reaction plasma processing chamber through fluid. The preliminary reaction plasma processing chamber is constituted so as to generate reaction radicals, by subjecting to chemical reaction based on the plasma of a reaction substance. The wafer plasma processing chamber is constituted so as to allow reaction radicals to react with the seeds on the surface of a wafer arranged in the wafer plasma processing chamber. Another example includes a method for processing a wafer in a plasma environment, pre-loading a reactive gaseous flow and previously preventing the erosion of a wafer mask or an etching stop layer. COPYRIGHT: (C)2004,JPO&NCIPI