公开(公告)号：JPH1131797A

公开(公告)日：1999-02-02

申请号：JP15505798

申请日：1998-06-03

Applicant: IBM

Inventor： MARK C HEIKY ,  DAVID V HORAK ,  MANDELMAN JACK A ,  WENDEL P NOBLE

IPC: H01L27/04 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/108

Abstract: PROBLEM TO BE SOLVED: To obtain a built-in strap structure which makes a device transfer gate longer in length by the use of a smaller cell region by a method wherein the inside of a storage trench is connected to the rear of an array transfer device, and the strap is arranged in a region which is used only for isolation. SOLUTION: An empty region inside a shallow trench isolation region 82 for a built-in strap which avoids a deep trench collar is used. The layout of a built-in strap indicated by an arrow 80 is carried out in a shallow trench isolation region 82. A space inside a transfer gate 84 between deep trenches 86 is not affected by the built-in strap. By this setup, a built-in strap structure which gives a longer device transfer gate length by the use of a smaller cell region can be obtained.

公开(公告)号：JP2000036596A

公开(公告)日：2000-02-02

申请号：JP11771499

申请日：1999-04-26

Applicant: IBM

Inventor： FURUKAWA TOSHIHARU ,  MARK C HEIKY ,  STEPHEN J HOLMES ,  DAVID V HORAK

IPC: H01L29/78 ,  H01L21/223 ,  H01L21/28 ,  H01L21/32 ,  H01L21/336 ,  H01L21/8238 ,  H01L27/092

Abstract: PROBLEM TO BE SOLVED: To form a narrow gate and a shallow expansion part by providing a layer (substrate) including one polysilicon gate and one source/drain region, and by simultaneously doping one gate stack and the source/drain region. SOLUTION: Vapor-phase doping is selectively used, and a polysilicon gate and an S/D region are simultaneously doped. Especially, a gate stack 20 and a well 18 that are not doped are covered with an appropriate diffusion prevention material 40. An S/D region 19 and a polysilicon gate 24 are exposed to n- and p-type gases or a doping source 30 of plasma. The gases can be variously changed corresponding to p and n types. For example, arsine AsH3 is used as arsenic trichloride AsCl3, phosphine PH3, and n-type gas dopant. When a masked laser beam is used, a diffusion prevention material 40 is eliminated, and reaction is repeated for the remaining stack 20 and the S/D region 19 by a type opposite to the doping source being used firstly.

公开(公告)号：MY115933A

公开(公告)日：2003-09-30

申请号：MYPI19994296

申请日：1999-10-06

Applicant: IBM

Inventor： TOSHIHARU FURUKAWA ,  MARK C HAKEY ,  DAVID V HORAK ,  STEVEN J HOLMES ,  PAUL A RABIDOUX

IPC: H01L21/336 ,  G03F7/00 ,  G03F7/20 ,  H01L21/027 ,  H01L21/033 ,  H01L21/28 ,  H01L21/311 ,  H01L21/768

Abstract: THE PRESENT INVENTION OVERCOMES THE LIMITATIONS OF THE PRIOR ART TO ALLOW FOR THE CREATION OF SMALLER COMPONENTS FOR USE IN LOGIC CIRCUITS. THE INVENTION PROVIDES A NEW METHOD OF DEFINING AND FONNING FEATURES ON A SEMICONDUCTOR SUBSTRATE BY USING A LAYER OF MATERIAL (210, 1010), REFERRED TO AS A SHADOW MANDREL LAYER, TO CAST A SHADOW (319, 1119, 1508). A TROUGH (312, 1112, 1506) IS ETCHED IN THE SHADOW MANDREL LAYER. AT LEAST ONE SIDE OF THE TROUGH WILL BE USED TO CAST A SHADOW IN THE BOTTOM (313, 1113) OF THE TROUGH. A CONFORMALLY DEPOSITED PHOTORESIST (314, 1114) USED TO CAPTURE THE IMAGE OF THE SHADOW. THE IMAGE OF THE SHADOW IS USED TO DEFINE AND FORM A FEATURE. THIS ALLOWS FOR THE CREATION OF IMAGES ON THE SURFACE OF A WAFER (202, 1002, 1504) WITHOUT THE DIFFRACTION EFFECTS ENCOUNTERED IN CONVENTIONAL PHOTOLITHOGRAPHY. THIS ALLOWS FOR A REDUCED DEVICE SIZE AND INCREASED CHIP OPERATING SPEED.FIG. 1

公开(公告)号：SG80082A1

公开(公告)日：2001-04-17

申请号：SG1999005207

申请日：1999-10-21

Applicant: IBM

Inventor： TOSHIHARU FURUKAWA ,  MARK C HAKEY ,  STEVEN J HOLMES ,  DAVID V HORAK ,  PAUL A RABIDOUX

IPC: G03F7/00 ,  G03F7/20 ,  H01L21/027 ,  H01L21/033 ,  H01L21/28 ,  H01L21/311 ,  H01L21/768 ,  G03C5/58

Abstract: The present invention overcomes the limitations of the prior art to allow for the creation of smaller components for use in logic circuits. The invention provides a new method of defining and forming features on a semiconductor substrate by using a layer of material, referred to as a shadow mandrel layer, to cast a shadow. A trough is etched in the shadow mandrel layer. At least one side of the trough will be used to cast a shadow in the bottom of the trough. A conformally deposited photoresist is used to capture the image of the shadow. The image of the shadow is used to define and form a feature. This allows for the creation of images on the surface of a wafer without the diffraction effects encountered in conventional photolithography. This allows for a reduced device size and increased chip operating speed.

公开(公告)号：SG102552A1

公开(公告)日：2004-03-26

申请号：SG1999005103

申请日：1999-10-13

Applicant: IBM

Inventor： ARCHIBALD ALLEN ,  TOSHIHARU FURUKAWA ,  EDWARD F O'NEIL ,  MARK C HAKEY ,  ROGER A VERHELST ,  DAVID V HORAK

IPC: H01L21/336 ,  H01L21/768 ,  H01L27/11

Abstract: The present invention overcomes the difficulties found in the background art by providing a direct low resistive contact between devices on a semiconductor chip without excessive current leakage. Current leakage is prevented in the preferred design by using silicon on insulator (SOI) construction for the chip. By constructing the direct contact over an insulator, such as silicon dioxide, current leakage is minimized. The preferred embodiment uses silicide to connect a polysilicon gate to a doped region of the substrate. An alternative embodiment of the present invention provides for the use of conductive studs to electrically connect devices. An increased density of approximately twenty percent may be realized using the present invention.

公开(公告)号：SG87850A1

公开(公告)日：2002-04-16

申请号：SG1999005476

申请日：1999-11-05

Applicant: IBM

Inventor： TOSHIHARU FURUKAWA ,  MARK C HAKEY ,  STEVEN J HOLMES ,  DAVID V HORAK ,  PAUL A RABIDOUX

IPC: H01L21/28 ,  G03C5/00 ,  H01L21/027 ,  H01L21/302 ,  H01L21/32 ,  H01L21/60 ,  H01L21/768

Abstract: A method for forming contacts on an integrated circuit that are self-aligned with the wiring patterns of the integrated circuit. In the method a thicker lower layer of a first material and a thinner upper layer of a second material are formed on a substrate. The features of the metal wiring is patterned first on the upper layer. The wiring pattern trenches are etched through the thinner surface layer, and partially through the second, thicker layer. After the wiring pattern is etched, the contacts for the wiring layer are printed as line/space patterns which intersect the wiring pattern. The contact pattern is etched into the lower, thicker layer with an etch process that is selective to the upper thinner layer. The contact is only formed at the intersection point of the wiring image with the contact image, therefore the contact is self-aligned to the metal.

公开(公告)号：SG82025A1

公开(公告)日：2001-07-24

申请号：SG1999005186

申请日：1999-10-18

Applicant: IBM

Inventor： TOSHIHARU FURUKAWA ,  MARK C HAKEY ,  STEVEN J HOLMES ,  DAVID V HORAK ,  PAUL A RABIDOUX

IPC: H01L21/033 ,  H01L21/308 ,  H01L21/336 ,  H01L21/768 ,  H01L21/822 ,  H01L29/78

Abstract: The present invention provides a method for forming self-aligned spacers on the horizontal surfaces while removing spacer material from the vertical surfaces. The preferred method uses a resist that can be made insoluble to developer by the use of an implant. By conformally depositing the resist over a substrate having both vertical and horizontal surfaces, implanting the resist, and developing the resist, the resist is removed from the vertical surfaces while remaining on the horizontal surfaces. Thus, a self-aligned spacer is formed on the horizontal surfaces while the spacer material is removed from the vertical surfaces. This horizontal-surface spacer can then be used in further fabrication. The preferred method can be used in many different processes where there is exists a need to differentially process the vertical and horizontal surfaces of a substrate.

公开(公告)号：SG80083A1

公开(公告)日：2001-04-17

申请号：SG1999005326

申请日：1999-10-22

Applicant: IBM

Inventor： TOSHIHARU FURUKAWA ,  MARK C HAKEY ,  STEVEN J HOLMES ,  DAVID V HORAK ,  PAUL A RABIDOUX

IPC: H01L21/027 ,  H01L21/768 ,  H01L21/32

Abstract: The present invention provides for an improved method of creating vias and trenches during microchip fabrication. According to the invention, the vias and trenches are self-aligned during the photolithography process by using two layers of specially selected resists and exposing the resists such that the lower resist is exposed only where an opening has been formed in the upper resist layer. This self-aligning enables the vias to be printed as elongated shapes, which allows for the use of particularly effective image enhancement techniques. The invention further provides a simplified procedure for creating vias and trenches, in that only one etch step is required to simultaneously create both vias and trenches. An alternative embodiment of the invention allows looped or linked images, such as those printed using image enhancement techniques, to be trimmed to form isolated features.