公开(公告)号：CA1273274A

公开(公告)日：1990-08-28

申请号：CA508583

申请日：1986-05-07

Applicant: IBM

Inventor： BEYER KLAUS D ,  MAKRIS JAMES S ,  MENDEL ERIC ,  NUMMY KAREN A ,  OGURA SEIKI ,  RISEMAN JACOB ,  ROVEDO NIVO

IPC: H01L21/76 ,  H01L21/302 ,  H01L21/306 ,  H01L21/3065 ,  H01L21/3105 ,  H01L21/74 ,  H01L21/762 ,  H01L21/763 ,  H01L21/205

Abstract: A chemical-mechanical (chem-mech) method for removing SiO2 protuberances at the surface of a silicon chip, such protuberances including "bird heads". A thin etch stop layer of Si3N4 is deposited onto the wafer surface, which is then chem-mech polished with a SiO2 water based slurry. The Si3N4 acts as a polishing or etch stop barrier layer only on the planar portions of the wafer surface. The portions of the Si3N4 layer located on the top and at the sidewalls of the "bird' heads" and the underlying SiO2 protuberances are removed to provide a substantially planar integrated structure.

公开(公告)号：FR2279223A1

公开(公告)日：1976-02-13

申请号：FR7518145

申请日：1975-06-03

Applicant: IBM

Inventor： KOENIG WILFRIED G ,  MAKRIS JAMES S ,  MASTERS BURTON J

IPC: H01L29/73 ,  H01L21/265 ,  H01L21/331 ,  H01L21/74

Abstract: A method of ion implantation into a semiconductor substrate which comprises forming a layer of an electrically insulative material, such as silicon dioxide, on the substrate over the region to be ion implanted. Then, a beam of ions having sufficient energy to pass through the layer of insulative material and to penetrate into the substrate is directed at a particular portion of the insulative layer. Before proceeding further, at least the upper half of the insulative layer, and preferably all of the upper portion of the insulative layer, in excess of a remaining thickness of 100A, is removed by etching. Then, the substrate is heated whereby the ions are driven further into the substrate to form the selected ion implanted region.

公开(公告)号：CA1286572C

公开(公告)日：1991-07-23

申请号：CA534158

申请日：1987-04-08

Applicant: IBM

Inventor： FULTON INGE G ,  MAKRIS JAMES S ,  NASTASI VICTOR R ,  SCADUTO ANTHONY F ,  SHARTEL ANNE C

IPC: H01L21/76 ,  H01L21/74 ,  H01L21/762 ,  H01L21/763 ,  H01L21/31 ,  H01L21/311

Abstract: Disclosed is a process of growing a conformal and etch-resistant silicon dioxide on a surface by forming a conformal layer of polysilicon and subjecting the polysilicon to thermal oxidation to completely convert the polysilicon into (poly) silicon oxide. Disclosed also is a method of forming an isolation trench in a semiconductor substrate having a high integrity oxide sidewall. After forming the trench in the substrate surface using a suitable etch mask and RIE, a single (thermal) oxide or dual (thermal) oxide and (CVD) nitride liner is formed on all trench surfaces. A conformal layer of undoped polysilicon is then formed (by. e.g. LPCVD) on the liner. By subjecting to thermal oxidation, the polysilicon is completely converted into a conformal (poly) silicon oxide layer having a thickness about 2.5 times that of the polysilicon layer. The resulting (poly) silicon oxide has the conformality of CVD oxide and the high etch resistance of thermally grown oxide. Alternatively, prior to forming the (poly) silicon oxide, the polysilicon layer is removed from the trench floor and the substrate surface in order to limit volume expansion of the polysilicon to a single direction perpendicular to the trench walls. The trench is filled with oxide, epitaxial silicon, polysilicon, polymers or metal, as desired. For achieving substrate contact through the trench, the trench bottom is opened up by RIE. Polysilicon is deposited with in-situ doping at a high temperature to fill the trench and simultaneously diffuse the dopant from the polysilicon fill into the underlying substrate to form a channel stop.

公开(公告)号：CA1139015A

公开(公告)日：1983-01-04

申请号：CA349764

申请日：1980-04-14

Applicant: IBM

Inventor： BARILE CONRAD A ,  GOTH GEORGE R ,  MAKRIS JAMES S ,  NAGARAJAN ARUNACHALA ,  RAHEJA RAJ K

IPC: H01L29/73 ,  H01L21/033 ,  H01L21/265 ,  H01L21/331 ,  H01L21/76 ,  H01L21/8222 ,  H01L27/06 ,  H01L27/07 ,  H01L29/417 ,  H01L21/22

Abstract: BIPOLAR TRANSISTOR FABRICATION PROCESS WITH AN ION IMPLANTED EMITTER A very high current ion implanted emitter is formed in a diffused base. Windows are made through the silicon nitride and silicon dioxide layers to both the base contact and the emitter regions using a resist mask. These regions are than protected by resist and the collector contact window is opened through the remainder of the silicon dioxide layer to the reach through region. A screen oxide is grown in all the exposed areas after removal of the resist mask. A resist mask is applied which covers only the base and Schottky anode regions. Arsenic is then implanted through the exposed screened areas followed by an etch back step to remove the top damaged layer. With some remaining screen oxide serving as a cap, the emitter drive-in is done. FI 9-78-055

公开(公告)号：CA1034683A

公开(公告)日：1978-07-11

申请号：CA231476

申请日：1975-07-15

Applicant: IBM

Inventor： KOENIG WILFRIED G ,  MAKRIS JAMES S ,  MASTERS BURTON J

IPC: H01L29/73 ,  H01L21/265 ,  H01L21/331 ,  H01L21/74

Abstract: A method of ion implantation into a semiconductor substrate which comprises forming a layer of an electrically insulative material, such as silicon dioxide, on the substrate over the region to be ion implanted. Then, a beam of ions having sufficient energy to pass through the layer of insulative material and to penetrate into the substrate is directed at a particular portion of the insulative layer. Before proceeding further, at least the upper half of the insulative layer, and preferably all of the upper portion of the insulative layer, in excess of a remaining thickness of 100A, is removed by etching. Then, the substrate is heated whereby the ions are driven further into the substrate to form the selected ion implanted region.