公开(公告)号：JPH10289197A

公开(公告)日：1998-10-27

申请号：JP9034698

申请日：1998-04-02

Applicant: IBM

Inventor： ARIMILLI BABA ,  KAISER JOHN MICHAEL ,  KIM KYONGMEE L ,  MAULE WARREN EDWARD

IPC: G06F13/36 ,  G06F12/08 ,  G06F12/0879

Abstract: PROBLEM TO BE SOLVED: To attain the burst transfer of processor data to an I/O device by performing the intermediate cache emulation logic to snatch and process the processor commands requesting the communication with the I/O device. SOLUTION: The processors 10a to 10c control the accesses to a system memory card 46 and an I/O mezzanine bus 36 for a memory/I/O bus controller 30. The bus 36 is connected to one or more I/O bridges 40 via the data links 38a and 38b. The bridges 40 snatch the trigger commands, and the processors 10a to 10c request the communication with an I/O device 60. The I/O bridges 40a and 40b perform the intermediate cache emulation logic to attain the emulation type cache burst transfer of data to the device 60 via an I/O bus 50.

公开(公告)号：HK1015048A1

公开(公告)日：1999-10-08

申请号：HK99100005

申请日：1999-01-04

Applicant: IBM

Inventor： ARIMILLI L BABA ,  KAISER JOHN MICHAEL ,  KIM KYONGMEE ,  MAULE WARREN EDWARD

IPC: G06F13/36 ,  G06F12/08 ,  G06F12/0879 ,  G06F

公开(公告)号：SG70629A1

公开(公告)日：2000-02-22

申请号：SG1998000575

申请日：1998-03-17

Applicant: IBM

Inventor： ARIMILLI BABA ,  KAISER JOHN MICHAEL ,  KIM KYONGMEE L ,  MAULE WARREN EDWARD

IPC: G06F13/36 ,  G06F12/08 ,  G06F12/0879

公开(公告)号：SG66439A1

公开(公告)日：1999-07-20

申请号：SG1998000511

申请日：1998-03-12

Applicant: IBM

Inventor： KAISER JOHN MICHAEL ,  MAULE WARREN EDWARD ,  MIRABELLA ROBERT DOMINICK ,  VICTOR DAVID WAYNE

IPC: G06F12/04 ,  G06F5/00 ,  G06F7/76 ,  G06F13/40 ,  G06F13/00

Abstract: To present a consistent image of storage facilities to components in Bi-modal Endian PowerPC system enviromnents, provision is made for transferring data between system components in the appropriate Endian format. Endian conversion function can be incorporated into the memory controller subsystem by adding byte-lane swapping logic on the inbound and outbound I/O data paths. With this structure, inbound data from the processor and memory bus will be converted to true Little Endian order before being sent to I/O devices. Likewise, true Little Endian data from I/O devices targeted for the processor or memory is modified to reflect the PowerPC Little Endian byte ordering convention.