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    IMPROVED CMOS DIODES WITH DUAL GATE CONDUCTORS, AND METHODS FOR FORMING THE SAME
    2.
    发明公开
    IMPROVED CMOS DIODES WITH DUAL GATE CONDUCTORS, AND METHODS FOR FORMING THE SAME 有权
    VERBESSERTE CMOS-DIODEN MIT DOPPELGATE-LEITERN UND VERFAHREN ZU IHRER HERSTELLUNG

    公开(公告)号：EP2020029A4

    公开(公告)日：2009-09-09

    申请号：EP07761243

    申请日：2007-04-25

    Applicant: IBM

    Inventor： ONSONGO DAVID M ,  RAUSCH WERNER ,  YANG HAINING S

    IPC: H01L23/62 ,  H01L21/329 ,  H01L29/739 ,  H01L29/78

    CPC classification number: H01L29/7391 ,  H01L29/66356

    Abstract: The present invention provides an improved CMOS diode structure with dual gate conductors. Specifically, a substrate comprising a first n-doped region and a second p-doped region is formed. A third region of either n-type or p-type conductivity is located between the first and second regions. A first gate conductor of n-type conductivity and a second gate conductor of p-type conductivity are located over the substrate and adjacent to the first and second regions, respectively. Further, the second gate conductor is spaced apart and isolated from the first gate conductor by a dielectric isolation structure. An accumulation region with an underlying depletion region can be formed in such a diode structure between the third region and the second or the first region, and such an accumulation region preferably has a width that is positively correlated with that of the second or the first gate conductor.

    Abstract translation: 本发明提供了具有双栅极导体的改进的CMOS二极管结构。 具体而言，形成包括第一n掺杂区域和第二p掺杂区域的衬底。 n型或p型导电性的第三区域位于第一和第二区域之间。 n型导电的第一栅极导体和p型导电的第二栅极导体分别位于衬底之上并且与第一和第二区域相邻。 此外，第二栅极导体通过介电隔离结构与第一栅极导体隔开并隔离。 在第三区域与第二区域或第一区域之间的这种二极管结构中可以形成具有基础耗尽区的积聚区域，并且这种积聚区域的宽度优选地与第二或第一栅极 导体。

    METHODOLOGY FOR LAYOUT-BASED MODULATION AND OPTIMIZATION OF NITRIDE LINER STRESS EFFECT IN COMPACT MODELS
    3.
    发明申请
    METHODOLOGY FOR LAYOUT-BASED MODULATION AND OPTIMIZATION OF NITRIDE LINER STRESS EFFECT IN COMPACT MODELS 审中-公开
    用于基于布局的调制方法和精简模型中氮化物线应力效应的优化

    公开(公告)号：WO2007016183A3

    公开(公告)日：2008-12-18

    申请号：PCT/US2006029069

    申请日：2006-07-26

    Applicant: IBM ,  CHIDAMBARRAO DURESETI ,  JORDAN DONALD L ,  MCCULLEN JUDITH H ,  ONSONGO DAVID M ,  WAGNER TINA ,  WILLIAMS RICHARD Q

    Inventor： CHIDAMBARRAO DURESETI ,  JORDAN DONALD L ,  MCCULLEN JUDITH H ,  ONSONGO DAVID M ,  WAGNER TINA ,  WILLIAMS RICHARD Q

    IPC: G06F7/48

    CPC classification number: G06F17/5068 ,  G06F17/5036 ,  H01L29/7843

    Abstract: System and method for compact model algorithms (310-350) to accurately account for effects of layout-induced changes in nitride liner (260) stress in semiconductor devices (200). The layout- sensitive compact model algorithms (310-350) account for the impact of large layout variation on circuits by implementing algorithms for obtaining the correct stress response approximations and layout extraction algorithms for obtaining the correct geometric parameters that drive the stress response. In particular, these algorithms include specific information from search "buckets" that are directionally-oriented and include directionally-specific distance measurements for analyzing in detail the specific shape neighborhood of the semiconductor device. The algorithms are additionally adapted to enable the modeling and stress impact determination of a device having single stress liner film and dual-stress liners (260) (two different liner films that abut at an interface).

    Abstract translation: 用于紧凑模型算法（310-350）的系统和方法来准确地说明半导体器件（200）中氮化物衬垫（260）应力的布局引起的变化的影响。 布局敏感的紧凑模型算法（310-350）通过实现用于获得正确的应力响应近似和布局提取算法的算法来解决大布局变化对电路的影响，以获得驱动应力响应的正确几何参数。 特别地，这些算法包括来自定向定向的搜索“桶”的特定信息，并且包括用于详细分析半导体器件的特定形状邻域的定向特定的距离测量。 这些算法还适用于能够确定具有单个应力衬垫膜和双应力衬垫（260）（在界面处邻接的两个不同衬垫膜）的器件的建模和应力冲击测定。

    IMPROVED CMOS DIODES WITH DUAL GATE CONDUCTORS, AND METHODS FOR FORMING THE SAME
    4.
    发明申请
    IMPROVED CMOS DIODES WITH DUAL GATE CONDUCTORS, AND METHODS FOR FORMING THE SAME 审中-公开
    改进的具有双栅导体的CMOS二极管及其形成方法

    公开(公告)号：WO2007127770A3

    公开(公告)日：2008-11-13

    申请号：PCT/US2007067361

    申请日：2007-04-25

    Applicant: IBM ,  ONSONGO DAVID M ,  RAUSCH WERNER ,  YANG HAINING S

    Inventor： ONSONGO DAVID M ,  RAUSCH WERNER ,  YANG HAINING S

    IPC: H01L23/62

    CPC classification number: H01L29/7391 ,  H01L29/66356

    Abstract: The present invention provides an improved CMOS diode structure with dual gate conductors. Specifically, a substrate comprising a first n-doped region and a second p-doped region is formed. A third region of either n-type or p-type conductivity is located between the first and second regions. A first gate conductor of n-type conductivity and a second gate conductor of p-type conductivity are located over the substrate and adjacent to the first and second regions, respectively. Further, the second gate conductor is spaced apart and isolated from the first gate conductor by a dielectric isolation structure. An accumulation region with an underlying depletion region can be formed in such a diode structure between the third region and the second or the first region, and such an accumulation region preferably has a width that is positively correlated with that of the second or the first gate conductor.

    Abstract translation: 本发明提供了具有双栅极导体的改进的CMOS二极管结构。 具体地，形成包括第一n掺杂区域和第二p掺杂区域的衬底。 n型或p型导电性的第三区域位于第一和第二区域之间。 n型导电体的第一栅极导体和p型导电体的第二栅极导体分别位于衬底上并且分别邻近第一和第二区域。 此外，第二栅极导体通过介电隔离结构与第一栅极导体隔开并隔离。 可以在第三区域和第二区域或第一区域之间的这种二极管结构中形成具有底层耗尽区域的积聚区域，并且这样的累积区域优选地具有与第二或第一栅极的宽度正相关的宽度 导体。

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