公开(公告)号：US3900736A

公开(公告)日：1975-08-19

申请号：US43758574

申请日：1974-01-28

Applicant: IBM

Inventor： MICHAIL MICHEL S ,  WOODARD OLLIE C ,  YOURKE HANNON S

IPC: H05K3/00 ,  H01J37/147 ,  H01J37/304 ,  H01J37/305 ,  H01L21/027 ,  H01J37/00

CPC classification number: H01J37/147 ,  H01J37/3045

Abstract: A beam of charged particles is stepped from one predetermined position to another to form a desired pattern on a semiconductor wafer to which the beam is applied in accordance with a predetermined pattern. Instead of the beam being stepped to each of the predetermined positions, there is a dynamic correction for the deviation of the actual position from its predetermined position so that the beam is applied to the deviated position rather than the predetermined position whereby the pattern is written within the boundaries of the writing field as determined by the location of four registration marks, which are in four separate positions or points in the field. Through location of each of the four registration marks, the writing field is precisely defined. Writing fields may be interconnected by the sharing of registration marks enabling the construction of chips which are larger than a single writing field.

公开(公告)号：CA1299240C

公开(公告)日：1992-04-21

申请号：CA580377

申请日：1988-10-17

Applicant: IBM

Inventor： MICHAIL MICHEL S ,  WALSH JAMES LEO

IPC: H03K19/00 ,  H03K19/082 ,  H03K19/086 ,  H03K17/16

Abstract: Half Current Switch With Feedback of the Invention A half current switch comprising: at least one input transistor, a load resistance connected between a first voltage reference and the collector of the input transistor, a constant-current resistance connected between the emitter of the input transistor and a second voltage reference, and a feedback means including at least one feedback connected to the constant-current resistance. The feedback means further includes means for biasing the feedback transistor to drive a current through the constant current resistance which, when flowing, increases with an increasing main current and decreases with a decreasing main current through the input transistor. The feedback means thus causes a constant current to be drawn by the input transistor when it is conducting, thereby controlling the capacitance of the input transistor while maintaining the output level constant.

公开(公告)号：CA1016667A

公开(公告)日：1977-08-30

申请号：CA214984

申请日：1974-11-29

Applicant: IBM

Inventor： MICHAIL MICHEL S ,  WOODARD OLLIE C ,  YOURKE HANNON S

IPC: H05K3/00 ,  H01J37/147 ,  H01J37/304 ,  H01J37/305 ,  H01L21/027

Abstract: 1480561 Automatic control of particle beams INTERNATIONAL BUSINESS MACHINES CORP 8 Jan 1975 [28 Jan 1974] 817/75 Heading G3N In the use of a beam of charged particles {electrons}applied to a target, the latter being provided with reference markings 42 delineating four sided fields 40, the deviation of the markings for one field from their assumed positions as determined by control 17-19 is determined, and, on the basis of disclosed algebraic analysis, a set of parameters, determining the displacement and distortion of the actual field with respect to the assumed field, are evaluated and used so that, for each beam position in the assumed field, a correction is applied to define a corresponding position in the actual field, the correction of the assumed marking positions being their actual positions. The target may be a semi-conductor wafer, the beam being used to write a pattern on an electroresist, or on a silicon dioxide layer to enhance its etch rating, such that a single pattern may encompass a plurality of fields, or patterns on several levels may be written on one field, the correction ensuring correct registration. The pattern data from computer 19 is used to cause the electron beam 11 to be scanned, in accordance with the assumed field, (50), Fig. 3 (not shown) by magnetic deflection coils 23-26, voltages proportional to the instantaneous deflection currents being passed on lines 55, 56 to the correction circuit, Fig. 2 receiving also the determined values of the parameters for the field being scanned, the circuit calculating corresponding instantaneous deflection voltages which are applied to plates 31- 34 correcting the beam deflection for each point of the field from the assumed to the actual field (51, Fig. 3). The parameters A-H, Fig. 2 are received by the correction circuit in digital form, to be processed in multiplying, and normal d/a converters 58, 59, 62-67, Fig. 2. The correction allows for translation, magnification, rotation and/ or trapezoidal error in the field. A further electrostatic circuit, Fig. 7 (not shown) may be used in conjunction with the scan; which may be a raster, or with alternate X scans being in opposed senses; to provide corrections to ensure linearity, or a steady beam offset fed in via d/a converter (125). Magnetic deflection circuit, Fig. 6 (not shown). In accordance with digital input from control(18), or selected combination of the positive, and negative constant current sources (70-75) may be coupled to integrator (77, 84) providing a scanning waveform corrected for linearity by circuitry (85), and an auxiliary circuit receiving data from the control (18). Upon beam reversal at the end of a line, circuit (98, 95, 96) is active to ensure that the beam attains an end point determined by the input to d/a converter (96), an error signal from amplifier (95) controlling integrator (77, 84) at this time. Each marking, Fig. 5 (not shown), comprises orthogonal rows (43, 44) of depressions or raised portions, detected by the electron beam. The beam may be used to prepare engineering drawings on a CRT, or for electron beam welding or cutting, or for forming a mask.

公开(公告)号：CA2007410C

公开(公告)日：1995-01-17

申请号：CA2007410

申请日：1990-01-09

Applicant: IBM

Inventor： CAVALIERE JOSEPH R ,  CHAN ALAN K-J ,  MICHAIL MICHEL S

IPC: G11C8/16 ,  G11C11/411 ,  G11C11/40 ,  G11C11/407

Abstract: A semiconductor memory cell for selectively storing or outputting differential signals responsive to a SELECT signal supplied on a word line includes: a transistor pair having cross-coupled base-collector terminals and emitter terminals connected to a common reference potential; sensing means connected to each of the base-collector terminals in the transistor pair, each of the sensing means including (a) a first diode having a cathode connected to the base-collector terminal, (b) a second diode having an anode connected to the anode of the first diode and a cathode connected to the word line, and (c) means connected at the commonly connected anodes of the first and second diodes for amplifying the signal thereat; writing means connected to each of the transistors in the transistor pair, the writing means including a transistor having a base connected to the word line and a collector connected to the base-collector terminal; and means for supplying constant current to each of the base-collector terminals and to each of the commonly connected anodes of the first and second diodes. The memory cell permits read access or select while maintaining the voltages on the latch nodes stable.