公开(公告)号：DE3070658D1

公开(公告)日：1985-06-20

申请号：DE3070658

申请日：1980-12-12

Applicant: IBM

Inventor： ANANTHA NARASIPUR GUNDAPPA ,  BHATIA HARSARAN SINGH ,  WALSH JAMES LEO

IPC: H01L29/73 ,  H01L21/033 ,  H01L21/331 ,  H01L23/532 ,  H01L21/00 ,  H01L21/314

Abstract: A method for making a high performance bipolar transistor characterized by self-aligned emitter and base regions and minimized base and emitter contact spacing. The disclosed method comprises forming a recessed oxide-isolated structure having opposite conductivity epitaxial layer and substrate. Multiple layered mass of alternating silicon nitride and silicon dioxide layers are placed over the base region and over the collector reach-through region. Polycrystalline silicon is deposited between the mesas. The mesas are undercut-etched to expose the extrinsic base region which is ion implanted. Then, the mesas are removed to expose the emitter and intrinsic base regions as well as the collector reach-through regions. The latter exposed regions are ion implanted appropriately. Contacts are made directly to the emitter and collector reach-through regions and indirectly via the polysilicon to the base region.

公开(公告)号：DE3065767D1

公开(公告)日：1984-01-05

申请号：DE3065767

申请日：1980-07-10

Applicant: IBM

Inventor： ANANTHA NARASIPUR GUNDAPPA ,  CAVALIERE JOSEPH RICHARD ,  KONIAN RICHARD ROBERT ,  SRINIVASAN GURUMAKONDA ,  STOLLER HERBERT IVAN ,  WALSH JAMES LEO

IPC: H01L21/033 ,  H01L29/08 ,  H01L29/10 ,  H01L21/00

Abstract: A method for making a bipolar filamentary pedestal transistor having reduced base-collector capacitance attributable to the elimination of the extrinsic base-collector junction. Silicon is deposited upon a coplanar oxide-silicon surface in which only the top silicon surface of the buried collector pedestal is exposed through the oxide. Epitaxial silicon deposits only over the exposed pedestal surface while polycrystalline silicon deposits over the oxide surface. The polycrystalline silicon is etched away except in the base region. An emitter is formed in the base region and contacts are made to the emitter, base and collector regions.

公开(公告)号：GB1048012A

公开(公告)日：1966-11-09

申请号：GB2647463

申请日：1963-07-04

Applicant: IBM

Inventor： WALSH JAMES LEO

IPC: H03K19/086

Abstract: 1,048,012. Transistor switching circuits. INTERNATIONAL BUSINESS MACHINES CORPORATION. July 4, 1963, No. 26474/63. Heading H3T. A transistor has a load switchable between high and low resistance states and is arranged such that when the resistance state is high the transistor is saturated and when it is low it is unsaturated and carries a higher current. In Fig. 3, when the load transistors 20 and 60 are non-conducting transistor 23 is saturated and its emitter current flows to its base. If either or both transistors 20 or 60 are rendered conductive transistor 28 comes out of saturation and an output signal is available at the collectors 20 and/or 60 or at the collector of 28. The circuit may be inhibited by rendering conducting a transistor 68 so as to divert the emitter current supply from 28. An inverted output may be obtained from the collector of a further transistor 92 (Fig. 4, not shown) having its emitter connected to the base of 28, the further transistor being rendered conducting by the base current of 28 when the load transistors 20 and 60 are non-conducting. An " exclusive OR " circuit may be formed (Fig. 7) from two sub-circuits each comprising transistors 20, 28 and 68 with each input signal applied in parallel to the normal input of a respective one and the inhibit input of the other. No output current flows when both signals are " 0 " or both " 1 " but if either alone is " 1 " an output will be obtained from the common collector load of the transistors 20. Fig. 7 illustrates a 3-level circuit. When V IN is positive transistor 20 cuts off and - V appears at the output terminal. When V IN is near earth, transistor 100 becomes unsaturated and its current flows in the output circuit. If V IN is positive both transistors 100 and 28 become unsaturation and a higher current flows in the output circuit.

公开(公告)号：DE3879466T2

公开(公告)日：1993-09-16

申请号：DE3879466

申请日：1988-12-06

Applicant: IBM

Inventor： MICHAIL MICHEL SALIB ,  WALSH JAMES LEO

IPC: H03K19/00 ,  H03K19/082 ,  H03K19/086 ,  H03K17/16

Abstract: A half current switch comprising: at least one input transistor (16), a load resistance (42, 44) connected between a first voltage reference and the collector of the input transistor, a constant-current resistance (32) connected between the emitter of the input transistor and a second voltage reference, and a feedback means including at least one feedback connected to the constant-current resistance. The feedback means further includes means for biasing the feedback transistor (36) to drive a current through the constant current resistance (32) which, when flowing, increases with an increasing main current and decreases with a decreasing main current through the input transistor. The feedback means thus causes a constant current to be drawn by the input transistor (16) when it is conducting, thereby controlling the capacitance of the input transistor while maintaining the output level constant. In a preferred embodiment, the feedback means comprises a PNP transistor with its base connected t the collector of the input transistor, with its emitter connected to the first voltage reference, and with its collector connected to the emitter of the input transistor. The PNP transistor not only acts as a feedback device to control current, but also acts to prevent oscillations when a speed-up capacitor (54) is used in the circuit.

公开(公告)号：DE3068955D1

公开(公告)日：1984-09-20

申请号：DE3068955

申请日：1980-08-12

Applicant: IBM

Inventor： CAVALIERE JOSEPH RICHARD ,  HENLE ROBERT ATHANASIUS ,  KONIAN RICHARD ROBERT ,  WALSH JAMES LEO

IPC: H03K19/086 ,  H03K5/02 ,  H03K17/04 ,  H03K17/60 ,  H03K17/66 ,  H03K19/082 ,  H03K19/20

Abstract: A complementary bipolar transistor circuit characterized by the same output impedance for positive and negative input voltage transitions, only a single collector path delay between input and output for both senses of input voltage transitions and very low standby power consumption. Provision is made for simultaneously actuating an emitter follower series-connected first pair of complementary transistors with signals having voltage swings which are only a fraction of the Vbe necessary to forward bias each base-emitter diode of the first pair of transistors. The actuation is accomplished using a second pair of complementary transistors having collector electrodes connected to respective bases of the first pair of transistors of similar kind. One of the remaining electrodes of each of the second pair of transistors are connected to each other. In a driver circuit species of the invention, the bases of the second pair of transistors are connected to each other and receive the input signal. In a logic circuit species of the invention, the emitter of one of the second pair of transistors is connected to the base of the other of the second pair of transistors. NOR logic is performed by connecting additional transistors in parallel with said one of the second pair of transistors, the bases of the additional transistors receiving respective logic input signals. The output from the driver circuit as well as from the logic circuit is derived from the commonly connected emitters of the first pair of transistors. The first pair of transistors conduct only during the transitions of the input signals.

公开(公告)号：DE2861136D1

公开(公告)日：1981-12-17

申请号：DE2861136

申请日：1978-09-06

Applicant: IBM

Inventor： ANANTHA NARASIPUR GUNDAPPA ,  BHATIA HARSARAN SINGH ,  WALSH JAMES LEO

IPC: H01L29/73 ,  H01L21/033 ,  H01L21/225 ,  H01L21/331 ,  H01L21/762 ,  H01L23/532 ,  H01L29/06 ,  H01L29/10 ,  H01L29/423 ,  H01L21/70 ,  H01L23/48

Abstract: A method for manufacturing a high performance bipolar device and the resulting structure which has a very small emitter-base spacing is described. The small emitter-base spacing, reduces the base resistance compared to earlier device spacing and thereby improves the performance of the bipolar device. The method involves providing a silicon semiconductor body having regions of monocrystalline silicon isolated from one another by isolation regions and a buried subcollector therein. A base region is formed in the isolated monocrystalline silicon. A mask is formed on the surface of the silicon body covering those regions designated to be the emitter and collector reach-through regions. A doped polycrystalline silicon layer is then formed through the mask covering the base region and making ohmic contact thereto. An insulating layer is formed over the polysilicon layer. The mask is removed from those regions designated to be the emitter and collector reach-through regions. The emitter junction is then formed in the base region and the collector reach-through formed to contact the buried subcollector. Electrical contacts are made to the emitter and collector. The doped polycrystalline silicon layer is the electrical contact to the base regions.

公开(公告)号：AU3844878A

公开(公告)日：1980-01-31

申请号：AU3844878

申请日：1978-07-28

Applicant: IBM

Inventor： ANANTHA NARASIPUR GUNDAPPA ,  BHATIA HARSARAN SINGH ,  WALSH JAMES LEO

IPC: H01L29/73 ,  H01L21/033 ,  H01L21/225 ,  H01L21/331 ,  H01L21/762 ,  H01L23/532 ,  H01L29/06 ,  H01L29/10 ,  H01L29/423 ,  H01L21/82 ,  H01L27/04 ,  H01L29/72 ,  H01L21/20 ,  H01L21/22 ,  H01L21/265 ,  H01L21/285 ,  H01L21/306 ,  H01L21/31

Abstract: A method for manufacturing a high performance bipolar device and the resulting structure which has a very small emitter-base spacing is described. The small emitter-base spacing, reduces the base resistance compared to earlier device spacing and thereby improves the performance of the bipolar device. The method involves providing a silicon semiconductor body having regions of monocrystalline silicon isolated from one another by isolation regions and a buried subcollector therein. A base region is formed in the isolated monocrystalline silicon. A mask is formed on the surface of the silicon body covering those regions designated to be the emitter and collector reach-through regions. A doped polycrystalline silicon layer is then formed through the mask covering the base region and making ohmic contact thereto. An insulating layer is formed over the polysilicon layer. The mask is removed from those regions designated to be the emitter and collector reach-through regions. The emitter junction is then formed in the base region and the collector reach-through formed to contact the buried subcollector. Electrical contacts are made to the emitter and collector. The doped polycrystalline silicon layer is the electrical contact to the base regions.

公开(公告)号：DE3879466D1

公开(公告)日：1993-04-22

申请号：DE3879466

申请日：1988-12-06

Applicant: IBM

Inventor： MICHAIL MICHEL SALIB ,  WALSH JAMES LEO

IPC: H03K19/00 ,  H03K19/082 ,  H03K19/086 ,  H03K17/16

Abstract: A half current switch comprising: at least one input transistor (16), a load resistance (42, 44) connected between a first voltage reference and the collector of the input transistor, a constant-current resistance (32) connected between the emitter of the input transistor and a second voltage reference, and a feedback means including at least one feedback connected to the constant-current resistance. The feedback means further includes means for biasing the feedback transistor (36) to drive a current through the constant current resistance (32) which, when flowing, increases with an increasing main current and decreases with a decreasing main current through the input transistor. The feedback means thus causes a constant current to be drawn by the input transistor (16) when it is conducting, thereby controlling the capacitance of the input transistor while maintaining the output level constant. In a preferred embodiment, the feedback means comprises a PNP transistor with its base connected t the collector of the input transistor, with its emitter connected to the first voltage reference, and with its collector connected to the emitter of the input transistor. The PNP transistor not only acts as a feedback device to control current, but also acts to prevent oscillations when a speed-up capacitor (54) is used in the circuit.

公开(公告)号：DE3062828D1

公开(公告)日：1983-05-26

申请号：DE3062828

申请日：1980-08-12

Applicant: IBM

Inventor： KONIAN RICHARD ROBERT ,  WALSH JAMES LEO

IPC: H03K19/086 ,  H03K5/02 ,  H03K17/04 ,  H03K17/60 ,  H03K17/66 ,  H03K19/013 ,  H03K19/20

Abstract: An emitter follower series-connected pair of complementary transistors (2,3) provide an output signal at the junction (20) between their commonly connected emitters. The NPN transistor (2) of the pair of transistors (2,3) is directly driven by an input signal applied to its base. The PNP transistor (3) of the pair of transistors (2,3) is driven through a series connection ofa NPN transistor (1) and a Schottky diode (4), the base of the NPN transistor (1) also receiving said input signal. The forward voltage of the Schottky diode (4) is less than the voltage Vbe of the PNP transistor (3). The PNP transistor (3) nominally is held off and conducts only on negative-going input signal transitions to discharge the capacitive load (6). The NPN transistor (2) of the pair of transistors conducts only on positive-going input signal transitions to charge the capacitive load (6). The circuit (14) which has a low power dissipation and a fast response for driving capacitive loads can be extended (15,16) to perform NOR logic and to provide a pair of output signals in phase opposition to each othar.

公开(公告)号：DE2861897D1

公开(公告)日：1982-07-29

申请号：DE2861897

申请日：1978-12-16

Applicant: IBM

Inventor： ANANTHA NARASIPUR GUNDAPPA ,  HENLE ROBERT ATHANASIUS ,  WALSH JAMES LEO

IPC: H01L27/04 ,  H01L21/822 ,  H01L23/52 ,  H01L23/64 ,  H01L29/8605 ,  H03K19/00 ,  H03K19/018 ,  H01L23/56 ,  H03K19/08 ,  H01L29/86

Abstract: A small variable resistor is used as a precision terminating resistor in an integrated circuit interconnection structure. The structure involves the use of a driver circuit connected to and driving a plurality of loads which are connected to a transmission line. The transmission line is terminated by the precision variable terminating resistor. The last load in the series of loads is located in the integrated circuit chip which has the variable terminating resistor. The absolute value of the variable resistor is difficult to control. The absolute value of any conventional integrated resistor is hard to control in manufacturing. However, by making the value of the resistance proportional to a voltage which itself is proportional to a deviation from a reference voltage, it is possible to obtain a much more precise value of resistance.