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公开(公告)号：EP1547165A4
公开(公告)日：2009-05-27
申请号：EP03773062
申请日：2003-09-26
Applicant: IBM
Inventor： AVOURIS PHAEDON , COHEN GUY MOSHE , MARTEL RICHARD , MISEWICH JAMES A , TSANG JAMES CHEN-HSIANG
CPC classification number: H01L51/52 , B82Y10/00 , H01L51/0048 , H01L51/0545 , Y10S977/742 , Y10S977/938 , Y10S977/949
Abstract: A light emitting device comprises a gate electrode (101), a channel (103) comprising a molecule for electrically stimulated optical emission, wherein the molecule is disposed within an effective range of the gate electrode (101), a source (104) coupled to a first end of the channel injecting electrons into the channel, and a drain (105) coupled to a second end of the channel injecting holes into the channel.
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Patent Agency Ranking
公开(公告)号：JP2004119970A
公开(公告)日：2004-04-15
申请号：JP2003305482
申请日：2003-08-28
Applicant: Internatl Business Mach Corp
, インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation Inventor： MISEWICH JAMES A , REOHR WILLIAM ROBERT , SCHROTT ALEJANDRO GABRIEL , RIIKON WAN
IPC: G11C11/22 , H01L21/28 , H01L21/336 , H01L21/8246 , H01L21/8247 , H01L27/105 , H01L27/115 , H01L29/78 , H01L29/788 , H01L29/792
CPC classification number: H01L27/11502 , G11C11/22 , H01L21/28291 , H01L27/11507 , H01L27/11585 , H01L27/1159 , H01L29/6684 , H01L29/78391
Abstract: PROBLEM TO BE SOLVED: To provide a ferroelectric gate field-effect tranisistor and a nonvolatile memory architecture, formed using it. SOLUTION: A vertical ferroelectric gate field-effect transistor (FeGFET) is provided with a substrate and a first drain/source electrode formed on the top surface of the substrate. A conductive channel region is formed on the top surface of the first drain/source electrode, and electrically connected to it. The FeGFET device is further provided with a ferroelectric gate region formed on at least one sidewall of the channel region, at least one gate electrode electrically contacting the ferroelectric gate region, and a second drain/source electrode, formed on the top surface of the channel region and electrically contacts the channel region. The ferroelectric gate region can be selectively polarized, depending on the potential supplied between the gate electrode and at least one of first and second drain/source electrode. A nonvolatile memory array, provided with a plurality of FeGFET device, is formed. COPYRIGHT: (C)2004,JPO
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3.发明专利Field-effect transistor structure having double layer perovskite oxide electrode and method for forming it 有权具有双层氧化铝氧化物电极的场效应晶体管结构及其形成方法
公开(公告)号：JP2003031815A
公开(公告)日：2003-01-31
申请号：JP2002110272
申请日：2002-04-12
Inventor： MISEWICH JAMES A , RAMESH RAMAMOORTHY , SCHROTT ALEJANDRO G
IPC: H01L21/28 , H01L21/306 , H01L21/336 , H01L29/417 , H01L29/786 , H01L39/22 , H01L49/00
CPC classification number: H01L49/003
Abstract: PROBLEM TO BE SOLVED: To provide an oxide channel FET structure for incorporating a buried oxide channel by incorporating conductive metallic oxide electrodes for buried source and drain electrodes.
SOLUTION: A method for constructing the oxide electrodes for use in an oxide channel field-effect transistor (OxFET) device is disclosed. The electrodes are formed by first depositing a double layer 130 and 140 of conducting perovskite oxides onto an insulating oxide substrate. A resist pattern with the electrode configuration is then defined over the double layer. The top oxide layer is ion milled to a depth without reaching the substrate. Chemical etching of RIE is used to remove the part of the lower conductive oxide layer. The source and drain electrodes are thereby defined, which can be then used as buried contacts.
COPYRIGHT: (C)2003,JPOAbstract translation: 要解决的问题：提供一种用于通过引入用于埋入的源极和漏极的导电金属氧化物电极来引入掩埋氧化物沟道的氧化物沟道FET结构。 解决方案：一种用于构建用于氧化物沟道场效应晶体管（OxFET）器件的氧化物电极的方法。 电极通过首先将导电钙钛矿氧化物的双层130和140首先沉积到绝缘氧化物衬底上而形成。 然后在双层上限定具有电极构型的抗蚀剂图案。 将顶部氧化物层离子研磨至深度而不到达基底。 使用RIE的化学蚀刻去除下部导电氧化物层的一部分。 源极和漏极由此被限定，其然后可以用作埋入触点。
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公开(公告)号：WO2004030043A2
公开(公告)日：2004-04-08
申请号：PCT/US0330647
申请日：2003-09-26
Applicant: IBM
Inventor： AVOURIS PHAEDON , COHEN GUY MOSHE , MARTEL RICHARD , MISEWICH JAMES A , TSANG JAMES CHEN-HSIANG
CPC classification number: H01L51/52 , B82Y10/00 , H01L51/0048 , H01L51/0545 , Y10S977/742 , Y10S977/938 , Y10S977/949
Abstract: A light emitting device comprises a gate electrode (101), a channel (103) comprising a molecule for electrically stimulated optical emission, wherein the molecule is disposed within an effective range of the gate electrode (101), a source (104) coupled to a first end of the channel injecting electrons into the channel, and a drain (105) coupled to a second end of the channel injecting holes into the channel.
Abstract translation: 发光装置包括栅电极（101），包含用于电激发光发射的分子的通道（103），其中分子设置在栅电极（101）的有效范围内，源（104）耦合到 所述沟道的第一端将电子注入所述沟道中，以及与所述沟道的第二端连接的漏极（105）将空穴注入所述沟道中。
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公开(公告)号：AU2003279724A8
公开(公告)日：2004-04-19
申请号：AU2003279724
申请日：2003-09-26
Applicant: IBM
Inventor： MISEWICH JAMES A , COHEN GUY MOSHE , TSANG JAMES CHEN-HSIANG , MARTEL RICHARD , AVOURIS PHAEDON
Abstract: A light emitting device comprises a gate electrode, a channel comprising a molecule for electrically stimulated optical emission, wherein the molecule is disposed within an effective range of the gate electrode, a source coupled to a first end of the channel injecting electrons into the channel, and a drain coupled to a second end of the channel injecting holes into the channel.
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公开(公告)号：AU2003279724A1
公开(公告)日：2004-04-19
申请号：AU2003279724
申请日：2003-09-26
Applicant: IBM
Inventor： COHEN GUY MOSHE , MARTEL RICHARD , MISEWICH JAMES A , TSANG JAMES CHEN-HSIANG , AVOURIS PHAEDON
Abstract: A light emitting device comprises a gate electrode, a channel comprising a molecule for electrically stimulated optical emission, wherein the molecule is disposed within an effective range of the gate electrode, a source coupled to a first end of the channel injecting electrons into the channel, and a drain coupled to a second end of the channel injecting holes into the channel.
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