公开(公告)号：JP2006215592A

公开(公告)日：2006-08-17

申请号：JP2004311995

申请日：2004-10-27

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： DOERING ANDREAS C ,  DRAGONE SILVIO ,  HERKERSDORF ANDREAS ,  HOFMANN RICHARD G ,  KUHLMANN CHARLES E

IPC: G06F9/30 ,  G06F9/38 ,  G06F9/54

Abstract: PROBLEM TO BE SOLVED: To provide a method and device for dynamically programming FPGA during execution of an application. SOLUTION: The method for dynamically programming FPGA (field programmable gate array)210 in a co-processor connected to a processor comprises steps of starting execution of the application by the processor; receiving an instruction which requests execution of a function for the application from the processor by the co-processor; determining that the FPGA in the co-processor is not programmed with a function logic; fetching a configuration bit stream for function; and programming the FPGA with the configuration bit stream 220. Therefore, the FPGA can be dynamically programmed during execution of the application. The application can further frequently use advantages of acceleration and resource sharing by hardware provided by the FPGA. COPYRIGHT: (C)2006,JPO&NCIPI

Abstract translation: 要解决的问题：提供在应用程序执行期间动态编程FPGA的方法和设备。 解决方案：在与处理器连接的协处理器中动态编程FPGA（现场可编程门阵列）210）的方法包括由处理器开始执行应用程序的步骤; 从协处理器接收从处理器请求执行应用功能的指令; 确定协处理器中的FPGA未用功能逻辑编程; 获取配置位流的功能; 并使用配置位流220对FPGA进行编程。因此，FPGA可以在应用程序执行期间动态编程。 该应用可以进一步经常使用FPGA提供的硬件加速和资源共享的优势。 版权所有（C）2006，JPO＆NCIPI

公开(公告)号：CA2160499A1

公开(公告)日：1996-05-31

申请号：CA2160499

申请日：1995-10-13

Applicant: IBM

Inventor： BLAND PATRICK M ,  CRONIN DANIEL R III ,  HOFMANN RICHARD G ,  MOELLER DENNIS ,  VENARCHICK LANCE M

IPC: G06F12/06 ,  G06F13/28 ,  G06F13/36 ,  G06F13/40 ,  G06F12/02

Abstract: A computer system that has two buses with different memory addressing capacitiesand a first bus master that generates M-bit addresses is provided with a bridge between the two buses. In order to generate N-bit addresses for use on the second bus, a direct memory access (DMA) controller on the bridge produces P bits, where P + M = N. The P bits are concentrated with the M bits to form an N-bit address used on the second bus to address memory. The addition of P bits reallocates the memory segment addressable by the M-bits to any location within the memory map addressable by an N-bit address.

公开(公告)号：BR9505209A

公开(公告)日：1997-09-16

申请号：BR9505209

申请日：1995-11-17

Applicant: IBM

Inventor： BLAND PATRICK MAURICE ,  CRONIN DANIEL R ,  HOFMANN RICHARD G ,  MOELLER DENNIS ,  VENARCHICK LANCE M

IPC: G06F12/06 ,  G06F13/28 ,  G06F13/36 ,  G06F13/40

Abstract: A computer system that has two buses (30, 32) with different memory addressing capacities and a first bus master (36) that generates M-bit addresses is provided with a bridge (34) between the two buses. In order to generate N-bit addresses for use on the second bus (30), a direct memory access (DMA) controller (50) on the bridge produces P bits, where P + M = N. The P bits are concentrated with the M bits to form an N-bit address used on the second bus (30) to address memory (40). The addition of P bits reallocates the memory segment addressable by the M-bits to any location within the memory map addressable by an N-bit address.

公开(公告)号：CA2124031A1

公开(公告)日：1994-11-29

申请号：CA2124031

申请日：1994-05-20

Applicant: IBM

Inventor： AMINI NADER ,  BLAND PATRICK M ,  BOURY BECHARA F ,  HOFMANN RICHARD G ,  LOHMAN TERENCE J

IPC: G06F13/28 ,  G06F13/30 ,  G06F13/36 ,  G06F13/40 ,  G06F13/14

Abstract: A direct memory access (DMA) support mechanism is provided for use in a computer system 10 which comprises (i) a central processing unit (CPU) 24 connected to system memory 32 by a first system bus 36, and a second system bus 16 connected to the CPU; (ii) a host bridge 20 connecting the second system bus to a peripheral bus 22; (iii) an input/output (I/O) bridge 78 connecting the peripheral bus to a standard I/O bus 92, the standard I/O bus having a plurality of standard I/O devices 90 attached thereto; and (v) arbitration logic 42 which functions in an arbitration mode for arbitrating between the plurality of standard I/O devices competing for access to the standard I/O bus, and in a grant mode wherein a selected standard I/O device is granted access to the standard I/O bus. The DMA support mechanism comprises a direct memory access (DMA) controller 40 for performing DMA cycles on behalf of the selected standard I/O device, and direct memory access (DMA) support logic for enabling the DMA cycles to be performed over the peripheral bus. The DMA support logic includes sideband signals directly connecting the DMA controller with the I/O bridge, the sideband signals including information identifying the bus size of the selected I/O device for which the DMA controller is performing the DMA cycles.

公开(公告)号：CA2118995A1

公开(公告)日：1994-11-29

申请号：CA2118995

申请日：1994-03-14

Applicant: IBM

Inventor： AMINI NADER ,  BLAND PATRICK M ,  BOURY BECHARA F ,  HOFMANN RICHARD G ,  LOHMAN TERENCE J

IPC: G06F13/36 ,  G06F13/362 ,  G06F13/364 ,  G06F13/40

Abstract: An arbitration mechanism 42 is provided for use in a computer system 10 which comprises (i) a central processing unit (CPU) 24; (ii) a first system bus 36 which connects the CPU 24 to system memory 32 so that the CPU 24 can read data from, and write data to, the system memory 32; (iii) a second system bus 16 connected to the CPU 24; (iv) a host bridge 20 connecting the second-system bus 16 to a peripheral bus 22, the peripheral bus 22 having at least one peripheral device 18 attached thereto; and (v) an input/output (I/O) bridge 78 connecting the peripheral bus 22 to a standard I/O bus 92, the standard I/O bus 92 having a plurality of standard I/O devices 90 attached thereto. The arbitration mechanism 42 comprises (i) a first level 100 of logic for arbitrating between the plurality of standard I/O devices 90, wherein one standard I/O device 90 is selected from a plurality of the standard I/O devices 90 competing for access to the standard I/O bus 97, and (ii) a second level 102, 104 of logic for arbitrating between the selected standard I/O device 90, the CPU 24 and the at least one peripheral device 18, wherein one of the selected standard I/O device 90, the CPU 24 and the at least one peripheral device 18 is selected to access the peripheral bus 22. The arbitration mechanism 42 includes sideband signals which connect the first 100 and second levels 102, 104 of arbitration logic and include arbitration identification information corresponding to the selected standard I/O device 90.

公开(公告)号：BR9203650A

公开(公告)日：1993-04-27

申请号：BR9203650

申请日：1992-09-18

Applicant: IBM

Inventor： AMINI NADER ,  BOURY BECHARA F ,  LOHMAN TERENCE J ,  BRANNON SHERWOOD ,  CONCILIO IAN A ,  HOFMANN RICHARD G

IPC: G06F13/00

公开(公告)号：CA2071301A1

公开(公告)日：1993-04-16

申请号：CA2071301

申请日：1992-06-16

Applicant: IBM

Inventor： AMINI NADER ,  BOURY BECHARA F ,  BRANNON SHERWOOD ,  HOFMANN RICHARD G ,  LOHMAN TERENCE J

IPC: G06F13/00 ,  G06F11/00 ,  G06F11/14 ,  G06F11/20 ,  G06F13/28 ,  G06F13/12

Abstract: BC9-91-079 ERROR DETECTION AND RECOVERY IN A DMA CONTROLLER A DMA controller with error circuitry which detects DMA error conditions is disclosed. The error circuitry causes the DMA controller to perform completion tasks before terminating a DMA transfer, advantageously providing a DMA controller which may exit gracefully upon detection of an error condition with the potential of error recovery.