公开(公告)号：CA1133146A

公开(公告)日：1982-10-05

申请号：CA337643

申请日：1979-10-15

Applicant: IBM

Inventor： BALYOZ JOHN ,  CHANG CHI S ,  FOX BARRY C ,  GHAFGHAICHI MAJID ,  JEN TEH-SEN ,  MOONEY DONALD B ,  PALMIERI JOHN A

IPC: H01L21/822 ,  H01L21/82 ,  H01L23/528 ,  H01L27/04 ,  H01L27/118 ,  H05K1/16 ,  H05K3/10

Abstract: MASTER IMAGE CHIP ORGANIZATION TECHNIQUE OR METHOD Semiconductor chips are optimally structured to facilitate the maximum number of devices and circuits, and to facilitate fabrication of a wide variety of large scale integrated part numbers. Essentially, none of the semiconductor surface is dedicated for signal and power wiring channels. A master image wiring structure is provided which resides over the semiconductor surface and beneath a power surface. This master image wiring structure makes it possible to personalize the power and signal wiring for a multiple power surface structure. The combined master image structure provides a means for optimally allocating semiconductor area for devices, functional units (micro and macro) and signal and power wiring to facilitate improved density and performance. FI9-78-014

公开(公告)号：CA1120606A

公开(公告)日：1982-03-23

申请号：CA326113

申请日：1979-04-23

Applicant: IBM

Inventor： BALYOZ JOHN ,  CHANG CHI S ,  FOX BARRY C ,  GHAFGHAICHI MAJID ,  JEN TEH-SEN ,  MOONEY DONALD B ,  PALMIERI JOHN A

IPC: H01L21/822 ,  H01L21/3205 ,  H01L21/82 ,  H01L23/52 ,  H01L23/528 ,  H01L27/04 ,  H01L27/118 ,  H01L27/10

Abstract: Disclosed is an improved masterslice design technique including structure, wiring, and method of fabricating, to provide improved Large Scale Integrated Devices. In accordance with the improved masterslice technique a plurality of semiconductor chips are provided wherein essentially the entire semiconductor surface area of each chip is utilized to provide cells selectable to be personalized (wired). None of the semiconductor surface area is dedicated for wiring channels. The individual cell area and cell configuration is optimally arrived at to facilitate wiring the maximum number, if not all of the cells contained on each chip, whereby circuit density is materially improved and a wide variety LSI device part numbers may be readily fabricated.