公开(公告)号：JP2006221622A

公开(公告)日：2006-08-24

申请号：JP2006016958

申请日：2006-01-25

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： FLEISCHER BRUCE M ,  HAESS JUERGEN ,  KROENER MICHAEL ,  MARTIN S SHUMUUKURAA ,  SCHWARZ ERIC M ,  DAO-TRONG SON

IPC: G06F7/76

CPC classification number: G06F7/483 ,  G06F7/499 ,  G06F7/49936 ,  G06F7/49947 ,  G06F7/5443 ,  G06F2207/382

Abstract: PROBLEM TO BE SOLVED: To improve performance of a floating point unit which performs feedback prior to normalization or rounding. SOLUTION: This system is for performing floating point arithmetic operation including an input register adapted for receiving an operand. This system further includes a mechanism for performing shifting or masking operation in response to determination that the operand is a un-normalization format. The system further includes an instruction for performing single-precision increment of the operand in response to determination that the operand is single-precision, that the operand requires the incrementing based on the result of previous operation and that the previous operation has not performed the incrementing. The operand is created in the previous operation. The system further includes an instruction for performing double precision incrementing of the operand in response to determination that the operand is double precision, that the operand requires the incrementing based on the result of the previous operation and that the previous operation has not performed the incrementing. COPYRIGHT: (C)2006,JPO&NCIPI

Abstract translation: 要解决的问题：提高在归一化或舍入之前执行反馈的浮点单元的性能。

解决方案：该系统用于执行浮点运算，包括适于接收操作数的输入寄存器。 该系统还包括用于响应于操作数是非归一化格式的确定而执行移位或掩蔽操作的机制。 该系统还包括响应于确定操作数是单精度来执行操作数的单精度增量的指令，操作数基于先前操作的结果需要增加，并且先前的操作没有执行递增 。 操作数是在上一操作中创建的。 该系统还包括响应于确定操作数是双精度来执行操作数的双精度递增的指令，操作数基于先前操作的结果需要增加，并且先前的操作未执行递增。 版权所有（C）2006，JPO＆NCIPI

公开(公告)号：DE19851690A1

公开(公告)日：2000-05-11

申请号：DE19851690

申请日：1998-11-10

Applicant: IBM

Inventor： GERWIG GUENTER ,  HAESS JUERGEN ,  KROENER MICHAEL ,  PFEFFER ERWIN

IPC: G06F7/72 ,  G06F11/08 ,  H03M7/02 ,  G06F11/30

Abstract: The method involves computing the modulo residues of corresponding numerical values before and after the conversion and comparing the corresponding residue values after the conversion. The numerical values are computer data. The first format can be a decimal number and the second format can be a binary number.

公开(公告)号：GB2506871A

公开(公告)日：2014-04-16

申请号：GB201218112

申请日：2012-10-10

Applicant: IBM

Inventor： LAYER CHRISTOPHE ,  MUELLER SILVIA MELITTA ,  KROENER MICHAEL ,  SCHELM KERSTIN

IPC: G06F7/544 ,  G06F7/49

Abstract: An arithmetic operation, such as an SRT computation of a division, square root, addition, subtraction or multiplication, in a data processing unit (216), preferably by iterative digit accumulations, is proposed. An approximate result of the arithmetic operation is computed iteratively. Concurrently, at least two supplementary values of the approximate result of the arithmetic operation are computed, and the final result selected from one of the values of the approximate result and the at least two supplementary values of the arithmetic operation depending on the results of the last iteration step. A multiplexing unit may select the final result. Iteration may use accumulating digit values concatenated to previous results using a radix.

公开(公告)号：GB2527125A

公开(公告)日：2015-12-16

申请号：GB201410591

申请日：2014-06-13

Applicant: IBM

Inventor： SCHELM KERSTIN ,  MUELLER SILVIA MELITTA ,  NIEKISCH MANUELA ,  KROENER MICHAEL

IPC: G06F7/487 ,  G06F7/537

Abstract: A method for performing an arithmetic operation in a data processing unit, including calculating a number of iterations 10 for performing the arithmetic operation with a given number of bits per iteration 12, wherein the number of bits per iteration 12 is a positive natural number; the method comprises counting a number of consecutive digit positions 32 of a digit in a sequence of bits 16 represented in the data processing unit, wherein the length of the sequence 16 is a multiple of the number of bits per iteration 12; and calculating a quotient of the number of consecutive digit positions 32 divided by the number of bits per iteration 12, as well as calculating a remainder of the division. The invention further relates to a data processing unit as well as a data processing system for execution of a data processing program comprising software code portions for performing said method.