公开(公告)号：US3584362A

公开(公告)日：1971-06-15

申请号：US3584362D

申请日：1969-03-12

Applicant: IBM

Inventor： HAZEL HERBERT K ,  MUELLER WOLFGANG F

IPC: G11C5/05 ,  G11C5/12 ,  G11C11/06 ,  H01R4/14 ,  H05K13/06 ,  H05K13/00 ,  B23P19/04 ,  H01F7/06

CPC classification number: H01R4/14 ,  G11C5/05 ,  G11C5/12 ,  G11C11/06 ,  H05K13/06 ,  Y10T29/49069 ,  Y10T29/49838 ,  Y10T29/53087 ,  Y10T29/53165 ,  Y10T29/53191 ,  Y10T29/53696 ,  Y10T29/53974

Abstract: THIS SPECIFICATION DESCRIBES THE WIRING OF FERRITE CORE MATRICES. FIRST A NUMBER OF WIRES WITH APERTURED FERRITE ELEMENTS STRUNG ON THEM ARE ARRANGED SIDE BY SIDE TO FORM COLUMNS OF FERRITE ELEMENTS AND SLIDE BACK AND FORTH ON THE WIRES. THEREAFTER, ONE ELEMENT ON EACH LENGTH OF WIRE IS ADVANCED TO A WIRING POSITION TO FORM A FIRST SELECTED ROW OF FERRITE ELEMENTS. THEN A ROW WIRE IS INSERTED THROUGH THE FERRITE ELEMENTS IN THE FIRST SELECTED ROW. AFTER THE ROW WIRE IS INSERTED, THE FERRITE ELEMENTS OF THE ROW ARE TESTED. ONCE THE FERRITE CORES IN THE FIRST SELECTED ROW TEST GOOD, THE PROCESS IS REPEATED FOR A SECOND ROW. PREFERABLY, THE SELECTED ROW OF FERRITE ELEMENTS IS HELD IN POSITION BY AIR DIRECTED AT THE ELEMENTS.

公开(公告)号：US3460245A

公开(公告)日：1969-08-12

申请号：US3460245D

申请日：1965-04-30

Applicant: IBM

Inventor： HAZEL HERBERT K ,  MUELLER WOLFGANG F

IPC: G11C5/05 ,  G11C5/12 ,  G11C11/06 ,  H01R4/14 ,  H05K13/06 ,  H01F7/06 ,  B23P19/04

CPC classification number: H01R4/14 ,  G11C5/05 ,  G11C5/12 ,  G11C11/06 ,  H05K13/06 ,  Y10T29/49004 ,  Y10T29/49069 ,  Y10T29/49838 ,  Y10T29/53022 ,  Y10T29/53087 ,  Y10T29/53165 ,  Y10T29/53696

公开(公告)号：DE3682871D1

公开(公告)日：1992-01-23

申请号：DE3682871

申请日：1986-09-16

Applicant: IBM

Inventor： MUELLER WOLFGANG F ,  SPENCER II GWYNNE W

IPC: H01L25/18 ,  H01L25/10 ,  H01L25/11

公开(公告)号：CA1229411A

公开(公告)日：1987-11-17

申请号：CA473184

申请日：1985-01-30

Applicant: IBM

Inventor： MUELLER WOLFGANG F ,  SPENCER GWYNNE W II

IPC: H01L25/18 ,  G11C5/00 ,  G11C11/21 ,  G11C11/401 ,  H01L23/48 ,  H01L23/50 ,  H01L25/10 ,  H01L25/11 ,  H01L27/10 ,  H05K7/10 ,  G11C5/06 ,  G11C5/04

Abstract: Stacked Double Density Memory Module Using Industry Standard Memory Chips A stacked double density memory module may be formed from two industry standard memory chips, by jumpering the no-connect and chip enable pins on one chip and then stacking the jumpered chip on the other chip with the pins on the jumpered (top) chip contacting the corresponding pins on the other (bottom) chip except for the chip select pins. In a preferred embodiment for use with 64K or one megabit DRAMs, the top chip is jumpered with a U-shaped strap which runs from the no-connect pin to the chip enable pin. The chip enable pin is bent toward the chip body to retain the strap in place. The technique may also be employed for stacking other industry standard memory or array chips.

公开(公告)号：CA1088218A

公开(公告)日：1980-10-21

申请号：CA299581

申请日：1978-03-22

Applicant: IBM

Inventor： MCKENNA CHARLES M ,  MUELLER WOLFGANG F

IPC: H01J37/20 ,  H01J37/02 ,  H01J37/244 ,  H01J37/317 ,  H01L21/265 ,  H01J37/00

Abstract: ION IMPLANTATION APPARATUS WITH A COOLED STRUCTURE CONTROLLING THE SURFACE POTENTIAL OF A TARGET SURFACE In an ion beam apparatus a structure for controlling the surface potential of the target comprising an electron source adjacent to the beam for providing electrons to the beam and means between the target and source for inhibiting rectilinear radiations, i.e., electron and other particle and photon radiations between said source and said target. This prevents heating of the target by the electron source and cross-contamination between the source and the target. The apparatus further includes means for maintaining said shield means at a lower temperature than said target. A further structure is provided for the measurement of the ion beam current while controlling said surface potential of the target which includes: walls adjacent to and electrically insulated from the target and surrounding the beam whereby the walls and target provide a Faraday Cage, means for introducing variable quantities of electrons into the beam within the Faraday Cage, means for measuring the target current, means for combining and measuring the target and wall currents to provide said ion beam current measurement and means for varying the quantities of introduced electrons to control the target current and thereby the target surface potential. Likewise, this apparatus further includes means for maintaining said shielding means at a temperature lower than said target.

公开(公告)号：CA846998A

公开(公告)日：1970-07-14

申请号：CA846998D

Applicant: IBM

Inventor： MUELLER WOLFGANG F ,  HAZEL HERBERT K