公开(公告)号：EP2419931A4

公开(公告)日：2012-04-04

申请号：EP10764802

申请日：2010-03-18

Applicant: IBM

Inventor： CAMPI JOHN B ,  CHANG SHUNHUA T ,  CHATTY KIRAN V ,  GAUTHIER ROBERT J ,  LI JUNJUN ,  MUHAMAD MUJAHID

IPC: H01L27/02

CPC classification number: H01L27/0274 ,  H01L2924/0002 ,  H01L2924/00

公开(公告)号：WO2010120428A3

公开(公告)日：2011-01-13

申请号：PCT/US2010027774

申请日：2010-03-18

Applicant: IBM ,  CAMPI JOHN B ,  CHANG SHUNHUA T ,  CHATTY KIRAN V ,  GAUTHIER ROBERT J ,  LI JUNJUN ,  MUHAMAD MUJAHID

Inventor： CAMPI JOHN B ,  CHANG SHUNHUA T ,  CHATTY KIRAN V ,  GAUTHIER ROBERT J ,  LI JUNJUN ,  MUHAMAD MUJAHID

IPC: H01L23/60 ,  H01L21/336

CPC classification number: H01L27/0274 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A robust ESD protection circuit, method and design structure for tolerant and failsafe designs are disclosed. A circuit (200) includes a middle junction control circuit (250) that turns off a top NFET (225) of a stacked NFET electrostatic discharge (ESD) protection circuit (pad 215, ground 220, top NFET 225, bottom NFET 230, top resistor 235, and bottom resistor 240) during an ESD event.

Abstract translation: 公开了用于容错和故障安全设计的强大的ESD保护电路，方法和设计结构。 一个电路（200）包括一个中间结点控制电路（250），该中间结点控制电路（250）将堆叠的NFET静电放电（ESD）保护电路（焊盘215，接地220，顶部NFET 225，底部NFET 230，顶部）的顶部NFET（225） 电阻器235和底部电阻器240）。

公开(公告)号：CA2755284A1

公开(公告)日：2010-10-21

申请号：CA2755284

申请日：2010-03-18

Applicant: IBM

Inventor： CAMPI JOHN B ,  CHANG SHUNHUA T ,  CHATTY KIRAN V ,  GAUTHIER ROBERT J ,  LI JUNJUN ,  MUHAMAD MUJAHID

IPC: H01L23/60 ,  H01L21/336

Abstract: A robust ESD protection circuit, method and design structure for tolerant and failsafe designs are disclosed. A circuit (200) includes a middle junction control circuit (250) that turns off a top NFET (225) of a stacked NFET electrostatic discharge (ESD) protection circuit (pad 215, ground 220, top NFET 225, bottom NFET 230, top resistor 235, and bottom resistor 240) during an ESD event.

公开(公告)号：CA2755284C

公开(公告)日：2017-11-21

申请号：CA2755284

申请日：2010-03-18

Applicant: IBM

Inventor： CAMPI JOHN B ,  CHANG SHUNHUA T ,  CHATTY KIRAN V ,  GAUTHIER ROBERT J ,  LI JUNJUN ,  MUHAMAD MUJAHID

IPC: H01L23/60 ,  H01L21/336

Abstract: A robust ESD protection circuit, method and design structure for tolerant and failsafe designs are dis-closed. A circuit (200) includes a middle junction control circuit (250) that turns off a top NFET (225) of a stacked NFET electrostatic discharge (ESD) protection circuit (pad 215, ground 220, top NFET 225, bottom NFET 230, top resistor 235, and bottom resistor 240) during an ESD event.

公开(公告)号：AU2010236920B2

公开(公告)日：2014-02-27

申请号：AU2010236920

申请日：2010-03-18

Applicant: IBM

Inventor： CAMPI JOHN B ,  CHANG SHUNHUA T ,  CHATTY KIRAN V ,  GAUTHIER ROBERT J ,  LI JUNJUN ,  MUHAMAD MUJAHID

IPC: H01L21/336 ,  H01L23/60

Abstract: A robust ESD protection circuit, method and design structure for tolerant and failsafe designs are disclosed. A circuit (200) includes a middle junction control circuit (250) that turns off a top NFET (225) of a stacked NFET electrostatic discharge (ESD) protection circuit (pad 215, ground 220, top NFET 225, bottom NFET 230, top resistor 235, and bottom resistor 240) during an ESD event.