公开(公告)号：US3793090A

公开(公告)日：1974-02-19

申请号：US3793090D

申请日：1972-11-21

Applicant: IBM

Inventor： BARILE C ,  DOCKERTY R ,  NAGARAJAN A

IPC: H01L29/78 ,  H01L21/28 ,  H01L21/283 ,  H01L21/314 ,  H01L21/316 ,  H01L21/336 ,  H01L29/00 ,  H01L29/51 ,  H01L7/34

CPC classification number: H01L21/28185 ,  H01L21/28202 ,  H01L21/3144 ,  H01L29/00 ,  H01L29/513 ,  H01L29/518 ,  H01L29/66833 ,  Y10S148/003 ,  Y10S148/113 ,  Y10S148/114 ,  Y10S148/122

Abstract: Large threshold voltage shifts of silicon gate FET devices having a composite nitride-oxide gate dielectric are greatly reduced by subjecting the nitride to a dry oxygen annealing at temperatures between 970*-1,150*C prior to depositing the silicon gate electrode. Annealing at 1,050*C applied for a duration of one-half to one hour produces excellent results.

Abstract translation: 在沉积硅栅电极之前，通过使氮化物在970-1.150℃的温度下进行干氧退火，大大降低了具有复合氮化物 - 氧化物栅极电介质的硅栅极FET器件的大的阈值电压偏移。 在1050°C退火持续时间为半小时，产生出色的效果。

公开(公告)号：SE384761B

公开(公告)日：1976-05-17

申请号：SE7314793

申请日：1973-10-31

Applicant: IBM

Inventor： BARILE C A ,  DOCKERTY R C ,  NAGARAJAN A

IPC: H01L21/28 ,  H01L29/78 ,  H01L21/283 ,  H01L21/314 ,  H01L21/316 ,  H01L21/336 ,  H01L29/00 ,  H01L29/51

Abstract: Large threshold voltage shifts of silicon gate FET devices having a composite nitride-oxide gate dielectric are greatly reduced by subjecting the nitride to a dry oxygen annealing at temperatures between 970 DEG -1,150 DEG C prior to depositing the silicon gate electrode. Annealing at 1,050 DEG C applied for a duration of one-half to one hour produces excellent results.

公开(公告)号：BE805959A

公开(公告)日：1974-02-01

申请号：BE136586

申请日：1973-10-11

Applicant: IBM

Inventor： BARILE C A ,  DOCKERTY R C ,  NAGARAJAN A

IPC: H01L29/78 ,  H01L21/28 ,  H01L21/283 ,  H01L21/314 ,  H01L21/316 ,  H01L21/336 ,  H01L29/00 ,  H01L29/51 ,  H01L

Abstract: Large threshold voltage shifts of silicon gate FET devices having a composite nitride-oxide gate dielectric are greatly reduced by subjecting the nitride to a dry oxygen annealing at temperatures between 970 DEG -1,150 DEG C prior to depositing the silicon gate electrode. Annealing at 1,050 DEG C applied for a duration of one-half to one hour produces excellent results.