公开(公告)号：US3836992A

公开(公告)日：1974-09-17

申请号：US34181473

申请日：1973-03-16

Applicant: IBM

Inventor： ABBAS S ,  BARILE C ,  LANE R ,  LIU P

IPC: G11C17/00 ,  G11C16/04 ,  H01L21/8247 ,  H01L29/417 ,  H01L29/788 ,  H01L29/792 ,  H01L11/14

CPC classification number: G11C16/0433 ,  H01L29/7886

Abstract: A read-mostly memory cell is disclosed comprising a floating gate avalanche injection field effect transistor storage device equipped with an erasing electrode. The memory portion of the erasable storage devices comprises a P channel FET having a floating polycrystalline silicon gate separated from an N-doped substrate by a layer of silicon dioxide. The erasing portion of the device comprises an erasing electrode separated from the polycrystalline silicon floating gate by a thermally grown layer of silicon dioxide having a leakage characteristic which is low in the presence of low electrical fields and high in the presence of high electrical fields. The floating gate is heavily doped with boron which also partially dopes the thermally grown silicon dioxide layer. The floating gate is charged negatively by avalanche breakdown of the FET drain while the erase gate is grounded to the substrate. The floating gate is discharged (erased) upon the application of a positive pulse to the erase electrode with respect to the semiconductor substrate causing electrodes on the charged floating gate to leak through the thermal oxide to the erasing electrode.

Abstract translation: 公开了一种读出多数的存储单元，其包括配备有擦除电极的浮栅雪崩注入场效应晶体管存储装置。 可擦除存储装置的存储部分包括具有通过二氧化硅层与N掺杂衬底分离的浮置多晶硅栅极的P沟道FET。 器件的擦除部分包括通过热存储二氧化硅层与多晶硅浮置栅极分离的擦除电极，其具有在存在低电场的情况下具有低泄漏特性并且在存在高电场的情况下高的漏电特性。 浮置栅极重掺杂硼，其也部分地掺杂热生长的二氧化硅层。 浮动栅极由FET漏极的雪崩击穿负电，而擦除栅极接地到衬底。 相对于半导体衬底向擦除电极施加正脉冲时，浮栅被放电（擦除），使得带电浮栅上的电极通过热氧化物泄漏到擦除电极。

公开(公告)号：US3793090A

公开(公告)日：1974-02-19

申请号：US3793090D

申请日：1972-11-21

Applicant: IBM

Inventor： BARILE C ,  DOCKERTY R ,  NAGARAJAN A

IPC: H01L29/78 ,  H01L21/28 ,  H01L21/283 ,  H01L21/314 ,  H01L21/316 ,  H01L21/336 ,  H01L29/00 ,  H01L29/51 ,  H01L7/34

CPC classification number: H01L21/28185 ,  H01L21/28202 ,  H01L21/3144 ,  H01L29/00 ,  H01L29/513 ,  H01L29/518 ,  H01L29/66833 ,  Y10S148/003 ,  Y10S148/113 ,  Y10S148/114 ,  Y10S148/122

Abstract: Large threshold voltage shifts of silicon gate FET devices having a composite nitride-oxide gate dielectric are greatly reduced by subjecting the nitride to a dry oxygen annealing at temperatures between 970*-1,150*C prior to depositing the silicon gate electrode. Annealing at 1,050*C applied for a duration of one-half to one hour produces excellent results.

Abstract translation: 在沉积硅栅电极之前，通过使氮化物在970-1.150℃的温度下进行干氧退火，大大降低了具有复合氮化物 - 氧化物栅极电介质的硅栅极FET器件的大的阈值电压偏移。 在1050°C退火持续时间为半小时，产生出色的效果。

公开(公告)号：ZA7701835B

公开(公告)日：1978-11-29

申请号：ZA7701835

申请日：1977-03-28

Applicant: IBM

Inventor： BARILE C ,  BRILL R ,  REGH J ,  FORNERIS J

IPC: H01L21/306 ,  H01L21/033 ,  H01L21/22 ,  H01L21/223 ,  H01L21/265 ,  H01L21/266 ,  H01L21/331 ,  H01L29/73

CPC classification number: H01L21/033 ,  H01L21/223 ,  H01L21/266 ,  Y10S148/131 ,  Y10S148/143 ,  Y10S438/965

公开(公告)号：ZA771835B

公开(公告)日：1978-11-29

申请号：ZA771835

申请日：1977-03-28

Applicant: IBM

Inventor： BARILE C ,  BRILL R ,  REGH J ,  FORNERIS J

IPC: H01L21/306 ,  H01L21/033 ,  H01L21/22 ,  H01L21/223 ,  H01L21/265 ,  H01L21/266 ,  H01L21/331 ,  H01L29/73