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    SERIAL BUS INTERFACE AND METHOD FOR SERIALLY INTERCONNECTING TIME-CRITICAL DIGITAL DEVICES
    1.
    发明申请
    SERIAL BUS INTERFACE AND METHOD FOR SERIALLY INTERCONNECTING TIME-CRITICAL DIGITAL DEVICES 审中-公开
    串行总线接口和用于串行连接数字数字设备的方法

    公开(公告)号：WO2004111596A2

    公开(公告)日：2004-12-23

    申请号：PCT/EP2004050633

    申请日：2004-04-28

    Applicant: IBM ,  IBM DEUTSCHLAND ,  SAALMUELLER DR JUERGEN ,  NEUMANN MARTIN ,  PIETSCHMANN WALTER ,  KLINKE ERHARD

    Inventor： SAALMUELLER DR JUERGEN ,  NEUMANN MARTIN ,  PIETSCHMANN WALTER ,  KLINKE ERHARD

    IPC: G06F13/40 ,  G01L13/00

    CPC classification number: G06F13/4072

    Abstract: The disclosed serial bus interface keeps most the time a driver buffer of the bus master active, except of a defined interval where a response from the slave is expected. This guarantees that a request echo of a request packet sent from the master reflected on a far non-terminated end of the slave gets terminated. The traveling time for such signal echoes can be defined by the distance in wire length between the master and the slave and/or the electrical characteristics of the transmission line. The slave can receive the request packet, add some processing time and send a response delayed by a programmable delay element. The response packet can arrive at the master after a further traveling delay. At that time, the request echo is already terminated and does no more disturb the data transmission. A programmable delay clement moves the above mentioned interval exactly to that point where a response packet arrives at the master. After such response was received, the driver buffer gets activated again while an according driver buffer on the slave side gets deactivated. Due to an active termination, a response echo gets canceled after a further round trip. During that time, any input on a receiver buffer on the slave side is ignored.

    Abstract translation: 所公开的串行总线接口保持总线主机的驱动器缓冲器的大部分时间，除了预期来自从机的响应的定义的间隔之外。 这保证了从主机远端未被终止的端口反映的主机发出的请求报文的请求回应被终止。 这种信号回波的行进时间可以通过主机和从机之间的线长度和/或传输线的电气特性来定义。 从机可以接收请求分组，添加一些处理时间并发送延迟由可编程延迟单元延迟的响应。 响应包可以在进一步的行进延迟之后到达主机。 此时，请求回显已经被终止，不再干扰数据传输。 可编程延迟元件将上述间隔精确地移动到响应包到达主器件的那一点。 接收到这样的响应后，驱动程序缓冲区再次被激活，而从端的相应的驱动程序缓冲区被禁用。 由于主动终止，响应回波在进一步往返之后被取消。 在此期间，从机侧的接收缓冲区上的任何输入都被忽略。

    SERIAL BUS INTERFACE AND METHOD FOR SERIALLY INTERCONNECTINGTIME-CRITICAL DIGITAL DEVICES
    3.
    发明专利
    SERIAL BUS INTERFACE AND METHOD FOR SERIALLY INTERCONNECTINGTIME-CRITICAL DIGITAL DEVICES 未知

    公开(公告)号：CA2529132A1

    公开(公告)日：2004-12-23

    申请号：CA2529132

    申请日：2004-04-28

    Applicant: IBM

    Inventor： PIETSCHMANN WALTER ,  KLINKE ERHARD ,  NEUMANN MARTIN ,  SAALMUELLER JURGEN

    IPC: G06F13/40

    Abstract: The disclosed serial bus interface keeps most the time a driver buffer of th e bus master active, except of a defined interval where a response from the slave is expected. This guarantees that a request echo of a request packet sent from the master reflected on a far non-terminated end of the slave gets terminated. The traveling time for such signal echoes can be defined by the distance in wire length between the master and the slave and/or the electric al characteristics of the transmission line. The slave can receive the request packet, add some processing time and send a response delayed by a programmab le delay element. The response packet can arrive at the master after a further traveling delay. At that time, the request echo is already terminated and do es no more disturb the data transmission. A programmable delay clement moves th e above mentioned interval exactly to that point where a response packet arriv es at the master. After such response was received, the driver buffer gets activated again while an according driver buffer on the slave side gets deactivated. Due to an active termination, a response echo gets canceled aft er a further round trip. During that time, any input on a receiver buffer on th e slave side is ignored.

    6.
    发明专利
    未知

    公开(公告)号：DE19616753A1

    公开(公告)日：1996-12-12

    申请号：DE19616753

    申请日：1996-04-26

    Applicant: IBM

    Inventor： NEUMANN MARTIN ,  GOETZE VOLKMAR

    IPC: G06F13/36 ,  G06F13/38 ,  G06F13/12 ,  H04L29/06

    Abstract: The invention concerns a device and a process for controlling a data-transmission channel or data bus, in particular a data bus on which the data are transmitted in a bit-serial manner according to a predetermined transmission protocol or bus protocol. The large number of data buses which currently exist or will be developed in future with their proprietary data bus protocols requires a special control device for nearly every data bus. The present invention enables a plurality of data buses (101) to be controlled owing to the use of a hierarchical processor architecture with at least two processor levels (102, 103) which are each optimized for particular control tasks. The invention can be used for controlling a plurality of data buses on which data are transmitted according to different transmission protocols. The invention is particularly suitable for controlling a plurality of field data buses or field buses for general applications and in particular for controlling field buses in motor vehicles, such as, for example, an ABUS, CAN bus, SAE bus J1850 or VAN bus.

    8.
    发明专利
    未知

    公开(公告)号：DE19616346A1

    公开(公告)日：1996-12-12

    申请号：DE19616346

    申请日：1996-04-24

    Applicant: IBM

    Inventor： NEUMANN MARTIN ,  GOETZE VOLKMAR

    IPC: G06F12/00 ,  G06F3/14 ,  G09G1/16 ,  G09G5/00 ,  G06F13/14

    Abstract: The invention concerns a computer system with optimized control for the computer system display, in particular a computer system with an integrated video controller which requires only a few additional connection pins. The invention further concerns a process for sequencing access to an image data store. The computer system (100) comprises a central control unit (110), a display unit (120), a display unit control device (125), an image data store (130), a system bus (140) and means (150) for sequencing access to the image data store (130). The central control unit (110), the display unit control device (125) and the image data store (130) are connected to the system bus (140) of the computer system (100). The invention can be used in a plurality of computer systems, in particular wherever the use of economical and reliable computer systems is required, for example in motor vehicle technology.

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