中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

10 records (took 0.042 seconds)

    DEVICE FOR ADDRESS TRANSLATION
    1.
    发明专利
    DEVICE FOR ADDRESS TRANSLATION 未知

    公开(公告)号：CA981370A

    公开(公告)日：1976-01-06

    申请号：CA146795

    申请日：1972-07-11

    Applicant: IBM

    Inventor： BOGER KLAUS ,  GENG HELLMUTH R ,  GOETZE VOLKMAR ,  HAJDU JOHANN

    IPC: G06F12/10

    Abstract: In a microprogrammed processor, a pair of register means and an associative store are arranged to eliminate the need to translate, for each microinstruction, a logical address to a real address to access main storage. Translation is required only once for each program or machine level (macro) instruction. The real addresses of the first bytes of the current instruction and its operand(s) are stored in a first one of the register means and are normally incremented to access the remainder of the instruction and operands byte-by-byte. In addition, the first register means and incrementer can be used to access sequentially stored instructions in a program sequence without address translation. When a page boundary is crossed during said incrementing, the logical page address of the current instruction or operand (which is at the boundary) is read from the second register means and is incremented to form the logical address of the next sequential page. This new logical address is searched in the associative array. If a match occurs, the new logical address is stored in the second register means, and the corresponding real address is stored in the first register means. This hardware translate means significantly reduces translate time.

    3.
    发明专利
    未知

    公开(公告)号：DE3121562A1

    公开(公告)日：1983-01-05

    申请号：DE3121562

    申请日：1981-05-30

    Applicant: IBM DEUTSCHLAND

    Inventor： GOETZE VOLKMAR ,  POTZ GUENTHER

    IPC: G11C17/00 ,  H03K19/177

    Abstract: A programmable logic array (PLA) is comprised of double-personalized cells conventionally arranged in an AND and OR array. In order to activate redundant or Don't Care positions, i.e., array positions not being used for performing the respective PLA functions, control circuits are provided preceding the AND array as well as between the AND and the OR array. This allows an increase in the number of possible PLA functions to be performed by a given PLA thus providing PLA's with improved functional density. The control circuits essentially consist of two-stage AND-OR circuits being fully compatible with the AND and OR array technology of the PLA. For optimum utilization of the Don't Care positions and planes, each functional input can be switched to any discretionary functional line of the PLA. By providing an additional control line in the OR array, the control logic for the entire OR array is reduced to only two AND gates.

    5.
    发明专利
    未知

    公开(公告)号：DE19616753A1

    公开(公告)日：1996-12-12

    申请号：DE19616753

    申请日：1996-04-26

    Applicant: IBM

    Inventor： NEUMANN MARTIN ,  GOETZE VOLKMAR

    IPC: G06F13/36 ,  G06F13/38 ,  G06F13/12 ,  H04L29/06

    Abstract: The invention concerns a device and a process for controlling a data-transmission channel or data bus, in particular a data bus on which the data are transmitted in a bit-serial manner according to a predetermined transmission protocol or bus protocol. The large number of data buses which currently exist or will be developed in future with their proprietary data bus protocols requires a special control device for nearly every data bus. The present invention enables a plurality of data buses (101) to be controlled owing to the use of a hierarchical processor architecture with at least two processor levels (102, 103) which are each optimized for particular control tasks. The invention can be used for controlling a plurality of data buses on which data are transmitted according to different transmission protocols. The invention is particularly suitable for controlling a plurality of field data buses or field buses for general applications and in particular for controlling field buses in motor vehicles, such as, for example, an ABUS, CAN bus, SAE bus J1850 or VAN bus.

    6.
    发明专利
    未知

    公开(公告)号：DE2134816A1

    公开(公告)日：1973-02-01

    申请号：DE2134816

    申请日：1971-07-13

    Applicant: IBM DEUTSCHLAND

    Inventor： BOGER KLAUS ,  GOETZE VOLKMAR ,  GENG HELLMUTH R ,  HAJDU JOHANN

    IPC: G06F12/10 ,  G06F13/06

    Abstract: In a microprogrammed processor, a pair of register means and an associative store are arranged to eliminate the need to translate, for each microinstruction, a logical address to a real address to access main storage. Translation is required only once for each program or machine level (macro) instruction. The real addresses of the first bytes of the current instruction and its operand(s) are stored in a first one of the register means and are normally incremented to access the remainder of the instruction and operands byte-by-byte. In addition, the first register means and incrementer can be used to access sequentially stored instructions in a program sequence without address translation. When a page boundary is crossed during said incrementing, the logical page address of the current instruction or operand (which is at the boundary) is read from the second register means and is incremented to form the logical address of the next sequential page. This new logical address is searched in the associative array. If a match occurs, the new logical address is stored in the second register means, and the corresponding real address is stored in the first register means. This hardware translate means significantly reduces translate time.

    8.
    发明专利
    未知

    公开(公告)号：DE19616346A1

    公开(公告)日：1996-12-12

    申请号：DE19616346

    申请日：1996-04-24

    Applicant: IBM

    Inventor： NEUMANN MARTIN ,  GOETZE VOLKMAR

    IPC: G06F12/00 ,  G06F3/14 ,  G09G1/16 ,  G09G5/00 ,  G06F13/14

    Abstract: The invention concerns a computer system with optimized control for the computer system display, in particular a computer system with an integrated video controller which requires only a few additional connection pins. The invention further concerns a process for sequencing access to an image data store. The computer system (100) comprises a central control unit (110), a display unit (120), a display unit control device (125), an image data store (130), a system bus (140) and means (150) for sequencing access to the image data store (130). The central control unit (110), the display unit control device (125) and the image data store (130) are connected to the system bus (140) of the computer system (100). The invention can be used in a plurality of computer systems, in particular wherever the use of economical and reliable computer systems is required, for example in motor vehicle technology.

Patent Agency Ranking