公开(公告)号：JP2008269601A

公开(公告)日：2008-11-06

申请号：JP2008104478

申请日：2008-04-14

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： NGUYEN DUNG QUOC ,  BARARAMU SHINHAROI ,  LE HUNG QUI

IPC: G06F9/38

CPC classification number: G06F9/384 ,  G06F9/3838 ,  G06F9/3857 ,  G06F9/3861

Abstract: PROBLEM TO BE SOLVED: To provide a unified register renaming mechanism targeting various instruction types in a microprocessor. SOLUTION: This universal renaming mechanism renames addresses of the various instruction types, using single name structure. An instruction for updating a floating point register (FPR) can be thereby renamed together with an instruction for updating a general purpose register (GPR) or a vector multimedium extension (VMX) instruction register (VR), using the same renaming structure, because the number of states designed for the GPR is same to the number of states designed for the FPR and the GPR. Each address tag (DTAG) is allocated to one address, and a fixed point instruction is allocated to the next DTAG. Considerable amounts of silicon and electric power are saved by providing the single name structure for all the instruction types, in case of the universal renaming mechanism. COPYRIGHT: (C)2009,JPO&INPIT

Abstract translation: 要解决的问题：提供一种针对微处理器中的各种指令类型的统一的寄存器重命名机制。 解决方案：该通用重命名机制使用单一名称结构重命名各种指令类型的地址。 因此，可以使用相同的重命名结构将用于更新浮点寄存器（FPR）的指令与用于更新通用寄存器（GPR）或向量多媒体扩展（VMX）指令寄存器（VR））的指令一起重命名，因为 为GPR设计的状态数量与为FPR和GPR设计的状态数量相同。 每个地址标签（DTAG）被分配给一个地址，并且固定点指令被分配给下一个DTAG。 在通用重命名机制的情况下，为所有指令类型提供单一名称结构，节省了大量的硅和电力。 版权所有（C）2009，JPO＆INPIT

公开(公告)号：JP2008226236A

公开(公告)日：2008-09-25

申请号：JP2008035515

申请日：2008-02-18

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： NGUYEN DUNG QUOC ,  LE HUNG QUI

IPC: G06F15/78 ,  G06F9/38

CPC classification number: G06F9/3802 ,  G06F9/3012 ,  G06F9/3013 ,  G06F9/3814 ,  G06F9/3836 ,  G06F9/3851 ,  G06F9/3857 ,  G06F9/3885 ,  G06F9/3891 ,  G06F9/5061 ,  G06F2209/5012

Abstract: PROBLEM TO BE SOLVED: To provide a configurable microprocessor which combines a plurality of corelets into a single microprocessor core to handle high computing-intensive workloads.
SOLUTION: The process for forming the single microprocessor core first selects two or more corelets in the plurality of corelets. The process combines resources of the two or more corelets to form combined resources, wherein each combined resource comprises a larger amount of a resource available to each individual corelet. The process then forms a single microprocessor core from the two or more corelets by assigning the combined resources to the single microprocessor core, wherein the combined resources are dedicated to the single microprocessor core, and wherein the single microprocessor core processes instructions with the dedicated combined resources.
COPYRIGHT: (C)2008,JPO&INPIT

Abstract translation: 要解决的问题：提供一种可配置的微处理器，其将多个核心组合到单个微处理器核心中以处理高计算密集型工作负载。 解决方案：形成单个微处理器核心的过程首先选择多个堆芯中的两个或更多个堆芯。 该过程组合两个或更多个核心小区的资源以形成组合的资源，其中每个组合的资源包括更大量的可用于每个单个小堆的资源。 然后，该过程通过将组合的资源分配给单个微处理器核心而从两个或更多个核心小区形成单个微处理器核心，其中组合资源专用于单个微处理器核心，并且其中单个微处理器核心使用专用组合资源来处理指令 。 版权所有（C）2008，JPO＆INPIT

公开(公告)号：JP2006114036A

公开(公告)日：2006-04-27

申请号：JP2005294193

申请日：2005-10-06

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： CURRAN BRIAN WILLIAM ,  KONIGSBURG BRIAN R ,  HUNG QUI LE ,  ARNOLD LUICK DAVID ,  NGUYEN DUNG QUOC

IPC: G06F9/46 ,  G06F9/38

CPC classification number: G06F9/3853 ,  G06F9/30145 ,  G06F9/382 ,  G06F9/3851 ,  G06F9/3885

Abstract: PROBLEM TO BE SOLVED: To simultaneously execute a plurality of instructions, and thereby efficiently use hardware resources to increase the whole processor throughput.
SOLUTION: A resource vector representing a necessary resource is encoded to a resource field, and the resource field is decoded in the subsequent step in order to derive the resource vector. The resource field is stored in an instruction cache related to respective program instructions. A processor operates in a simultaneous multithreading mode. When validity of a resource is equal to or exceeds a resource requirement of an instruction group, instructions thereof are simultaneously dispatched to hardware resources. A starting bit is inserted into one of the program instructions in order to define the instruction group. The hardware resource is, in particular, an execution unit such as a fixed decimal point unit 56, a load/store unit 58, a floating decimal point unit 60 or a branch processing unit 61.
COPYRIGHT: (C)2006,JPO&NCIPI

Abstract translation: 要解决的问题：同时执行多个指令，从而有效地使用硬件资源来增加整个处理器的吞吐量。 解决方案：将表示必要资源的资源向量编码到资源字段，并且在后续步骤中对资源字段进行解码，以便导出资源向量。 资源字段存储在与各个程序指令相关的指令高速缓存中。 处理器以同时多线程模式运行。 当资源的有效性等于或超过指令组的资源需求时，其指令被同时发送到硬件资源。 为了定义指令组，将起始位插入其中一个程序指令。 硬件资源特别是诸如固定小数点单元56，加载/存储单元58，浮动小数点单元60或分支处理单元61之类的执行单元。（C）2006， JPO＆NCIPI

公开(公告)号：JP2002287957A

公开(公告)日：2002-10-04

申请号：JP2002042171

申请日：2002-02-19

Applicant: IBM

Inventor： LE HUNG QUI ,  NGUYEN DUNG QUOC

IPC: G06F9/30 ,  G06F9/34 ,  G06F9/38

Abstract: PROBLEM TO BE SOLVED: To provide a method and a device adaptable to the temporal request for the high frequency design and accessible to an operand in a single cycle. SOLUTION: An operand buffer having a plurality of entries in which each entry is allocated to the command in generation queues. The operand buffer has the entries of the same number as that of the generation queues. A designed register and a register file for temporary data are input. Data in the operand buffer is written from the register file when the entry is written. When the command is executed, the corresponding entry in the operand buffer is unnecessary, and the entry is dis-allocated. The operand buffer has only entries smaller in number than the register file. Thus, the operand access stage requires the reading of not the register file but the operand buffer, and the operand buffer is read in one cycle.

公开(公告)号：JP2000020307A

公开(公告)日：2000-01-21

申请号：JP14060199

申请日：1999-05-20

Applicant: IBM

Inventor： NGUYEN DUNG QUOC

IPC: G06F9/38

Abstract: PROBLEM TO BE SOLVED: To improve processor performance by completing much more instructions for each cycle. SOLUTION: Inside a super-scalar processor, each execution unit is provided with a related completion table and that table is provided with the copy in the status to be dispatched and of the all instructions not yet to be completed. A central completion table 132 holds the status of the all dispatched instructions reported by a dispatch unit and an individual execution unit. Further, an instruction capable of generating interruption and instruction capable of making the register of the same result as a target are retracted. The completion table related to the execution unit retracts the balance of the instructions and the execution unit transmits the instruction status to the central completion table 132 and each execution unit. As a result, the number of the instructions to be retracted by the central completion table 132 is reduced and the number of the instructions to be completed for each clock cycle is increased.

公开(公告)号：DE112012000965T8

公开(公告)日：2014-06-05

申请号：DE112012000965

申请日：2012-02-20

Applicant: IBM

Inventor： ABERNATHY CHRISTOPHER MICHAEL ,  LE HUNG QUI ,  NGUYEN DUNG QUOC ,  KAHLE JAMES ALLAN ,  EISEN SUSAN ELIZABETH ,  BROWN MARY DOUGLASS

IPC: G06F9/30 ,  G06F9/34 ,  G06F9/38 ,  G06F12/00

公开(公告)号：GB2502222A

公开(公告)日：2013-11-20

申请号：GB201314787

申请日：2012-02-20

Applicant: IBM

Inventor： ABERNATHY CHRISTOPHER MICHAEL ,  LE HUNG QUI ,  NGUYEN DUNG QUOC ,  BROWN MARY DOUGLASS ,  KAHLE JAMES ALLAN ,  EISEN SUSAN ELIZABETH

IPC: G06F9/30 ,  G06F9/38 ,  G06F9/46

Abstract: A system and process for managing thread transitions may include the ability to determine that a transition is to be made regarding the relative use of two data register sets and determine, based on the transition determination, whether to move thread data in at least one of the data register sets to second-level registers. The system and process may also include the ability to move the thread data from at least one data register set to second-level registers based on the move determination.

公开(公告)号：GB2502222B

公开(公告)日：2014-04-09

申请号：GB201314787

申请日：2012-02-20

Applicant: IBM

Inventor： ABERNATHY CHRISTOPHER MICHAEL ,  LE HUNG QUI ,  NGUYEN DUNG QUOC ,  BROWN MARY DOUGLASS ,  KAHLE JAMES ALLAN ,  EISEN SUSAN ELIZABETH

IPC: G06F9/30 ,  G06F9/38 ,  G06F9/46

Abstract: A system and process for managing thread execution includes providing two data register sets coupled to a processor and using, by the processor, the two register sets as first-level registers for thread execution. A portion of main memory or cache memory is assigned as second-level registers where the second-level registers serve as registers of at least one of the two data register sets for executing the threads. Data for the threads may be moved between the first-level registers and second-level registers for different modes of thread processing.

公开(公告)号：DE112012000965T5

公开(公告)日：2013-11-14

申请号：DE112012000965

申请日：2012-02-20

Applicant: IBM

Inventor： ABERNATHY CHRISTOPHER MICHAEL ,  LE HUNG QUI ,  NGUYEN DUNG QUOC ,  KAHLE JAMES ALLAN ,  EISEN SUSAN ELIZABETH ,  BROWN MARY DOUGLASS

IPC: G06F9/30 ,  G06F9/34 ,  G06F9/38 ,  G06F12/00

Abstract: Ein System und ein Prozess zum Verwalten von Thread-Übergängen kann die Fähigkeit beinhalten, zu ermitteln, dass ein Übergang im Hinblick auf die relative Nutzung von zwei Datenregistersätzen vorzunehmen ist, und auf der Grundlage der Übergangsermittlung zu ermitteln, ob Thread-Daten in mindestens einem der Datenregistersätze auf Register der zweiten Ebene zu verschieben sind. Das System und der Prozess können zudem die Fähigkeit beinhalten, die Thread-Daten auf der Grundlage der Verschiebeermittlung von mindestens einem Datenregistersatz auf Register der zweiten Ebene zu verschieben.

公开(公告)号：CA2271533C

公开(公告)日：2001-12-04

申请号：CA2271533

申请日：1999-05-12

Applicant: IBM

Inventor： NGUYEN DUNG QUOC

IPC: G06F9/38 ,  G06F9/30

Abstract: Each execution unit within a superscalar processor has an associated completion table that contains a copy of the status of all instructions dispatched but not completed. A central completion table maintains the status of every dispatched instruction as reported by th e dispatch unit and the individual execution units. Execution units send finish signals to the completion table responsible for retiring a particular type of instruction. The central completion table retires instructions that may cause an interrupt and instructions whose results may target the same register. The execution units' associated completion tables retire the balance of the instructions and the execution units send instruction status to the central completion table and to each execution uni t. This reduces the number of instructions that are retired by the central completion table,increasing the number of instructions retired per clock cycle.