公开(公告)号：DE112012000965T8

公开(公告)日：2014-06-05

申请号：DE112012000965

申请日：2012-02-20

Applicant: IBM

Inventor： ABERNATHY CHRISTOPHER MICHAEL ,  LE HUNG QUI ,  NGUYEN DUNG QUOC ,  KAHLE JAMES ALLAN ,  EISEN SUSAN ELIZABETH ,  BROWN MARY DOUGLASS

IPC: G06F9/30 ,  G06F9/34 ,  G06F9/38 ,  G06F12/00

公开(公告)号：DE112012000965T5

公开(公告)日：2013-11-14

申请号：DE112012000965

申请日：2012-02-20

Applicant: IBM

Inventor： ABERNATHY CHRISTOPHER MICHAEL ,  LE HUNG QUI ,  NGUYEN DUNG QUOC ,  KAHLE JAMES ALLAN ,  EISEN SUSAN ELIZABETH ,  BROWN MARY DOUGLASS

IPC: G06F9/30 ,  G06F9/34 ,  G06F9/38 ,  G06F12/00

Abstract: Ein System und ein Prozess zum Verwalten von Thread-Übergängen kann die Fähigkeit beinhalten, zu ermitteln, dass ein Übergang im Hinblick auf die relative Nutzung von zwei Datenregistersätzen vorzunehmen ist, und auf der Grundlage der Übergangsermittlung zu ermitteln, ob Thread-Daten in mindestens einem der Datenregistersätze auf Register der zweiten Ebene zu verschieben sind. Das System und der Prozess können zudem die Fähigkeit beinhalten, die Thread-Daten auf der Grundlage der Verschiebeermittlung von mindestens einem Datenregistersatz auf Register der zweiten Ebene zu verschieben.

公开(公告)号：GB2502222B

公开(公告)日：2014-04-09

申请号：GB201314787

申请日：2012-02-20

Applicant: IBM

Inventor： ABERNATHY CHRISTOPHER MICHAEL ,  LE HUNG QUI ,  NGUYEN DUNG QUOC ,  BROWN MARY DOUGLASS ,  KAHLE JAMES ALLAN ,  EISEN SUSAN ELIZABETH

IPC: G06F9/30 ,  G06F9/38 ,  G06F9/46

Abstract: A system and process for managing thread execution includes providing two data register sets coupled to a processor and using, by the processor, the two register sets as first-level registers for thread execution. A portion of main memory or cache memory is assigned as second-level registers where the second-level registers serve as registers of at least one of the two data register sets for executing the threads. Data for the threads may be moved between the first-level registers and second-level registers for different modes of thread processing.

公开(公告)号：GB2502222A

公开(公告)日：2013-11-20

申请号：GB201314787

申请日：2012-02-20

Applicant: IBM

Inventor： ABERNATHY CHRISTOPHER MICHAEL ,  LE HUNG QUI ,  NGUYEN DUNG QUOC ,  BROWN MARY DOUGLASS ,  KAHLE JAMES ALLAN ,  EISEN SUSAN ELIZABETH

IPC: G06F9/30 ,  G06F9/38 ,  G06F9/46

Abstract: A system and process for managing thread transitions may include the ability to determine that a transition is to be made regarding the relative use of two data register sets and determine, based on the transition determination, whether to move thread data in at least one of the data register sets to second-level registers. The system and process may also include the ability to move the thread data from at least one data register set to second-level registers based on the move determination.

公开(公告)号：DE69831906T2

公开(公告)日：2006-06-14

申请号：DE69831906

申请日：1998-08-25

Applicant: IBM

Inventor： EISEN SUSAN ELIZABETH ,  PHILLIPS JAMES EDWARD

IPC: G06F9/38

Abstract: An out-of-order issue mechanism for a data processing system allows two out-of-order instructions to be issued to independent "pipes" from a window of four instructions currently queued for execution. If the two pipes execute floating pipe operations, dependencies between a computationally intensive floating point unit instruction (referred to as an fpu rr instruction) and the two previous computational intensive instructions having a target and a floating point register (the "fpr target") are tracked to provide a mechanism that quickly determines when dependent data is available from one of the floating point unit pipes. The data is then used to preempt the issue of a dependent instruction until data is available. Additionally, this out-of-order issue mechanism recognizes when consecutive instructions are dependent upon a same operand. In this situation, the mechanism prioritizes the first of the two instructions to be issued to the pipe satisfying the dependency, while the second instruction is preempted in favor of issuing an independent instruction or an instruction whose dependent data has already been made available to the other pipe when such an instruction is waiting in a queue.

公开(公告)号：DE69831906D1

公开(公告)日：2005-11-24

申请号：DE69831906

申请日：1998-08-25

Applicant: IBM

Inventor： EISEN SUSAN ELIZABETH ,  PHILLIPS JAMES EDWARD

IPC: G06F9/38

Abstract: An out-of-order issue mechanism for a data processing system allows two out-of-order instructions to be issued to independent "pipes" from a window of four instructions currently queued for execution. If the two pipes execute floating pipe operations, dependencies between a computationally intensive floating point unit instruction (referred to as an fpu rr instruction) and the two previous computational intensive instructions having a target and a floating point register (the "fpr target") are tracked to provide a mechanism that quickly determines when dependent data is available from one of the floating point unit pipes. The data is then used to preempt the issue of a dependent instruction until data is available. Additionally, this out-of-order issue mechanism recognizes when consecutive instructions are dependent upon a same operand. In this situation, the mechanism prioritizes the first of the two instructions to be issued to the pipe satisfying the dependency, while the second instruction is preempted in favor of issuing an independent instruction or an instruction whose dependent data has already been made available to the other pipe when such an instruction is waiting in a queue.