公开(公告)号：JPH0621206A

公开(公告)日：1994-01-28

申请号：JP9569893

申请日：1993-04-22

Applicant: IBM

Inventor： JIYOOJI UIRIAMU DOTSURE ,  OGURA SEIKI ,  NIBUO ROBUEDO

IPC: H01L21/304 ,  H01L21/306 ,  H01L21/3105 ,  H01L21/321 ,  H01L21/76 ,  H01L21/762 ,  H01L27/12

Abstract: PURPOSE: To maintain the precision of the thickness of a grinding gage by stopping oxidization, when all the polysilicon has been converted into oxide at the time of forming device layers with certain intervals on an SOI wafer, and making a mesa thin, until it is equal to the height of the upper face of new oxide by chemical machinery type grinding. CONSTITUTION: An oxide layer 20 is provided on a bulk silicon substrate 10, and an epitaxial single-crystal device layer 30 is separated into a pair of mesas 40 by a pair of narrow trenches surrounding the maser and extending to the oxide layer 20, and a trench 32 is provided with an oxide bottom face. A pair of maser-separating trenches 32 are set, so as to be small such that the device intensity on a integrated circuit can be minimized, and a wide region such as a trench 35 can be prevented from tissing-processed. The thickness of the mesa 40 is decreased so as to be controlled precisely, and grinding is continued until the thickness of the mesa can equal the gate thickness of a layer 45, by using a layer equipped with two functions for precisely controlling the thickness for holding the upper face of a wafer to be flat.

公开(公告)号：JPH098159A

公开(公告)日：1997-01-10

申请号：JP13318396

申请日：1996-05-28

Applicant: IBM

Inventor： OGURA SEIKI ,  NIBUO ROBUEDO

IPC: H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

Abstract: PROBLEM TO BE SOLVED: To provide an integrated circuit including an EEPROM cell which can be formed in self-alignment manner with high integration density, whose coupling rate is increased, and whose operating margin is improved as a result. SOLUTION: In an integrated circuit which contains an EEPROM cell, the EEPROM cell contains a conduction channel region, a floating gate 50 which is insulated from the conduction channel region and a control gate electrode structure which is insulated from the conduction channel region and the floating gate and which is overlapped with the surface and the side face of the floating gate. The control gate electrode structure contains a control electrode 18 and a conductive sidewall 82 which is ohmic-connected to the control electrode.

公开(公告)号：JPH04276653A

公开(公告)日：1992-10-01

申请号：JP35108891

申请日：1991-12-11

Applicant: IBM

Inventor： MAIKERU MONKOUSUKI ,  SEIKI OGURA ,  NIBUO ROBUEDO ,  JIYOZEFU FURANSHISU SHIEPAADO

IPC: H01L27/06 ,  H01L21/225 ,  H01L21/763 ,  H01L21/8249

Abstract: PURPOSE: To easily assemble an integrated circuit device which uses circuit elements on the same chip by different technologies. CONSTITUTION: This process includes a state for forming part of a circuit element at the same time by both CMOS and bipolar technologies, a stage for making the circuit element by to the bipolar technology and partially completing the circuit element by the CMOS technology, a stage for masking the circuit element by the CMOS technology and completing the circuit element by the bipolar technology, and a stage for completing the circuit element by the CMOS technology. A self-aligning and self-making process is used at a maximum and several stages are performed at the same time for devices of different technologies to decrease the number of stages. Further, making stage in use has allowance for a position shift, so the manufacture yield becomes high.