公开(公告)号：AU2003278329A1

公开(公告)日：2004-06-23

申请号：AU2003278329

申请日：2003-10-22

Applicant: IBM

Inventor： NORSTRAND ALBERT JAMES VAN JR ,  FEISTE KURT ALAN ,  SHIPPY DAVID

IPC: G06F7/38 ,  G06F9/312 ,  G06F9/345 ,  G06F9/38 ,  G06F15/00

Abstract: A system and method is provided for improving throughput of an in-order multithreading processor. A dependent instruction is identified to follow at least one long latency instruction with register dependencies from a first thread. The dependent instruction is recycled by providing it to an earlier pipeline stage. The dependent instruction is delayed at dispatch. The completion of the long latency instruction is detected from the first thread. An alternate thread is allowed to issue one or more instructions while the long latency instruction is being executed.

公开(公告)号：GB2520503A

公开(公告)日：2015-05-27

申请号：GB201320537

申请日：2013-11-21

Applicant: IBM

Inventor： NORTH GERAINT ,  STARKE WILLIAM ,  NAYAR NARESH ,  NORSTRAND ALBERT JAMES VAN JR ,  GUTHRIE GUY LYNN

IPC: G06F11/14 ,  G06F9/455 ,  G06F11/20 ,  G06F12/08 ,  G06F12/0804 ,  G06F12/0806 ,  G06F12/0831 ,  G06F12/0855 ,  G06F12/128

Abstract: System comprising: a processor running a hypervisor for virtual machines (VMs); a cache, e.g. write-back cache; and a memory storing VM images and a log for a differential check-pointing failover. Cache rows comprise a memory address, cache line, and image modification flag. A cache controller sets the modification flag when a cache line is modified by a backed-up VM. Flagged cache lines addresses are written in the log upon eviction or during periodic checkpoints. The log is a circular buffer 200 and its free space is monitored, e.g. by a guard band. If the head of the log entries moves within the guard-band an interrupt is triggered and a cash flush initiated. This avoids full memory re-synch or failover if a consumer core cannot keep-up with a producer core. Replication of the VM image in another memory can be obtained by fetching the cache lines stored at the logged addresses.