公开(公告)号：EP0205809A2

公开(公告)日：1986-12-30

申请号：EP86105482

申请日：1986-04-21

Applicant: IBM

Inventor： BUCHHOLZ WERNER ,  SMITH RONALD M ,  WEHRLY DAVID S

IPC: G06F9/48 ,  G06F9/315 ,  G06F9/38 ,  G06F15/78 ,  G06F17/16 ,  G06F15/347

CPC classification number: G06F9/30032 ,  G06F9/30036 ,  G06F9/30065 ,  G06F9/325 ,  G06F15/8084

Abstract: A vector processor is disclosed which processes vectors that can have more elements than a vector register can contain at one time. Vectors are processed in sections in which the section size is determined by the number of element locations in a vector register. A vector count register controls the number of elements processed by each vector instruction. A vector interruption index points to the first or next element in a vector to be processed by a vector instruction either when it is first issued or when it is re-issued following an interruption of the vector instruction. A general purpose (length) register contains the entire length of the vector to be 1 processed. A single instruction, which starts a vector sectioning loop, provides for the smaller of the section size or the content of the length register to be loaded into the vector count register. During the operation of the sectioning loop, the vector count register is repetitively subtracted from the content of the first general purpose register and the resulting residual vector length is placed back in the first general purpose register until all of the elements have been processed.

公开(公告)号：JPS61290570A

公开(公告)日：1986-12-20

申请号：JP11099086

申请日：1986-05-16

Applicant: IBM

Inventor： BUCHHOLZ WERNER ,  SMITH RONALD M ,  WEHRLY DAVID S

IPC: G06F9/48 ,  G06F9/315 ,  G06F9/38 ,  G06F15/78 ,  G06F17/16

Abstract: A vector processor is disclosed which processes vectors that can have more elements than a vector register can contain at one time. Vectors are processed in sections in which the section size is determined by the number of element locations in a vector register. A vector count register controls the number of elements processed by each vector instruction. A vector interruption index points to the first or next element in a vector to be processed by a vector instruction either when it is first issued or when it is re-issued following an interruption of the vector instruction. A general purpose (length) register contains the entire length of the vector to be 1 processed. A single instruction, which starts a vector sectioning loop, provides for the smaller of the section size or the content of the length register to be loaded into the vector count register. During the operation of the sectioning loop, the vector count register is repetitively subtracted from the content of the first general purpose register and the resulting residual vector length is placed back in the first general purpose register until all of the elements have been processed.

公开(公告)号：CA2015214A1

公开(公告)日：1990-11-30

申请号：CA2015214

申请日：1990-04-23

Applicant: IBM

Inventor： BONO RICHARD C ,  BRANDT HENRY R ,  CAVAGNARO HAROLD F ,  LEE ARLIN E ,  NORTON DARWIN W JR ,  SHALKEY ERIC T ,  SILSBEE TERRENCE K ,  WEHRLY DAVID S ,  WILLIAMS CLIFFORD T ,  ZIMMERMAN TERRENCE K

IPC: G06F13/12 ,  G06F13/42 ,  G06F15/17

Abstract: The disclosed arrangement provides apparatus and method for implementing a High Speed Link (HSL) such as the newly proposed ANSI High-Speed Channel (HSC) standard on processors complexes like the IBM 3090 having a paging store with an independent bus. A high speed link adapter (HSLA) including input and output buffers and controls is coupled to the independent bus under program control. Program access to high speed link is obtained by an extension to the Page-in and Page-out instructions.

公开(公告)号：CA2015214C

公开(公告)日：1996-01-02

申请号：CA2015214

申请日：1990-04-23

Applicant: IBM

Inventor： BONO RICHARD C ,  BRANDT HENRY R ,  CAVAGNARO HAROLD F ,  LEE ARLIN E ,  NORTON DARWIN W JR ,  SHALKEY ERIC T ,  SILSBEE DAVID L ,  WEHRLY DAVID S ,  WILLIAMS CLIFFORD T ,  ZIMMERMAN TERRENCE K

IPC: G06F13/12 ,  G06F13/42 ,  G06F15/17 ,  G06F13/00

Abstract: This embodiment provides apparatus and method for implementing a High Speed Link (HSL) such as the newly proposed ANSI High Performance Parallel interface (HPPI) standard on processors complexes like the IBM? 3090TM having a paging store with an independent bus. A high speed link adapter (HSLA) including input and output buffers and controls is coupled to the independent bus under program control. Program access to high speed link is obtained by an extension to the Page-in and Page-out instructions.

公开(公告)号：CA1242281A

公开(公告)日：1988-09-20

申请号：CA501738

申请日：1986-02-12

Applicant: IBM

Inventor： BUCHHOLZ WERNER ,  SMITH RONALD M ,  WEHRLY DAVID S

IPC: G06F9/48 ,  G06F9/315 ,  G06F9/38 ,  G06F15/78 ,  G06F17/16 ,  G06F15/347

Abstract: VECTOR PROCESSING A vector processor is disclosed which processes vectors that can have more elements than a vector register can contain at one time. Vectors are processed in sections in which the section size is determined by the number of element locations in a vector register. A vector count register controls the number o' elements processed by each vector instruction. A vector interruption index points to the first or next element in a vector to be processed by a vector instruction either when it is first issued or when it is re-issued following an interruption of the vector instruction. A general purpose (length) register contains the entire length of the vector to be processed. A single instruction, which starts a vector sectioning loop, provides for the smaller of the section size or the content of the length register to be loaded into the vector count register. During the operation of the sectioning loop, the vector count register is repetitively subtracted from the content of the first general purpose register and the resulting residual vector length is placed back in the first general purpose register until all of the elements have been processed.