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公开(公告)号：SG44049A1
公开(公告)日：1997-11-14
申请号：SG1996010105
申请日：1996-06-19
Applicant: IBM
Inventor： CAMPBELL JEFFREY SCOTT , HERARD JAMES D , NOWAK RONALD PETER , SLACK JOHN ROBERT , STONE DAVID BRIAN
Abstract: A support structure is attached to the front or back side of a flexible circuit by direct mounting to the flexible circuit flat ribbon cable, thereby providing a stress-free region of the cable in which the flexible circuit electrical components can be mounted. The support structure comprises a flat ring that is attached to the cable by adhesive, soldering, or mechanical fastening. The flat ring mounts on one side of the flat ribbon cable and encloses an area of the cable that is sufficiently large for the mounting of the flexible circuit electrical components. The flat ribbon cable within the enclosed area is held flat and free from stress, even as the cable is handled. Thus, any components mounted within the enclosed area are not subjected to bending moments. The invention also can be incorporated into cable connectors, such as multi-pin connectors at the ends of cables, and can include support hooks and air cooling baffles.
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公开(公告)号：HK1010605A1
公开(公告)日：1999-06-25
申请号：HK98111590
申请日：1998-10-29
Applicant: IBM
Inventor： FEILCHENFELD NATALIE BARBARA , KRESGE JOHN STEVEN , MOORE SCOTT PRESTON , NOWAK RONALD PETER , WILSON JAMES WARREN
IPC: H01L21/48 , H01L21/60 , H01L23/12 , H01L23/14 , H01L23/498 , H05K1/05 , H05K3/40 , H05K3/46 , H01L , H05K
Abstract: The present invention provides an organic chip carrier particularly useful with flip chips. The chip carrier comprises an organic dielectric layer, a first layer of circuitry disposed on the dielectric layer, an organic conformational coating disposed over the first layer of dielectric and the first layer of circuitry, and a layer of fine line circuitry. The fine line circuitry has a line width of about 2.0 mil or less, preferably about 1.0 mil or less, and more preferably about 0.7 mil, and a space between lines of about 1.5 mil or less, preferably about 1.1 mil or less. Preferably the dielectric layer is free of woven fiber glass. The conformational coating preferably has a dielectric constant of about 1.5 to about 3.5, and a percent planarization of greater than about 30%. The invention also relates to methods of making the dielectric coated chip carrier.
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公开(公告)号：SG60177A1
公开(公告)日：1999-02-22
申请号：SG1997004679
申请日：1997-12-24
Applicant: IBM
Inventor： FEILCHENFELD NATALIE BARBARA , KRESGE JOHN STEVEN , MOORE SCOTT PRESTON , NOWAK RONALD PETER , WILSON JAMES WARREN
IPC: H01L21/48 , H01L21/60 , H01L23/12 , H01L23/14 , H01L23/498 , H05K1/05 , H05K3/40 , H05K3/46 , H05K1/18
Abstract: The present invention provides an organic chip carrier particularly useful with flip chips. The chip carrier comprises an organic dielectric layer, a first layer of circuitry disposed on the dielectric layer, an organic conformational coating disposed over the first layer of dielectric and the first layer of circuitry, and a layer of fine line circuitry. The fine line circuitry has a line width of about 2.0 mil or less, preferably about 1.0 mil or less, and more preferably about 0.7 mil, and a space between lines of about 1.5 mil or less, preferably about 1.1 mil or less. Preferably the dielectric layer is free of woven fiber glass. The conformational coating preferably has a dielectric constant of about 1.5 to about 3.5, and a percent planarization of greater than about 30%. The invention also relates to methods of making the dielectric coated chip carrier.
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Patent Agency Ranking
公开(公告)号：MY141640A
公开(公告)日：2010-05-31
申请号：MYPI9706319
申请日：1997-12-26
Applicant: IBM
Inventor： FEILCHENFELD NATALIE BARBARA , KRESGE JOHN STEVEN , MOORE SCOTT PRESTON , NOWAK RONALD PETER , WILSON JAMES WARREN
IPC: H01L23/495 , H01L21/48 , H01L21/60 , H01L23/04 , H01L23/12 , H01L23/14 , H01L23/48 , H01L23/498 , H01L23/52 , H05K1/05 , H05K3/40 , H05K3/46
Abstract: THE PRESENT INVENTION PROVIDES AN ORGANIC CHIP CARRIER (10) PARTICULARLY USEFUL WITH FLIP CHIPS (42), COMPRISING AN ORGANIC DIELECTRIC LAYER (22), A FIRST LAYER OF CIRCUITRY (25) DISPOSED ON THE DIELECTRIC LAYER, AN ORGANIC CONFORMATIONAL COATING (34) DISPOSED OVER THE FIRST LAYER OF DIELECTRIC AND THE FIRST LAYER OF CIRCUITRY, AND A LAYER OF FINE LINE CIRCUITRY (40) HAVING LINE WIDTH OF ABOUT 0. 0508 MM (2.0 MIL) OR LESS. PREFERABLY ABOUT 0.0254 MM (1.0 MIL) OR LESS, PREFERABLY ABOUT 0.01778 MM (0.7 MIL), AND A SPACE BETWEEN LINES OF ABOUT 0.0381 MM (1.5 MIL) OR LESS, PREFERABLY ABOUT 0.02794 MM (1.1 MIL) OR LESS, DISPOSED ON THE CONFORMATIONAL LAYER. PREFERABLY THE DIELECTRIC LAYER IS FREE OF WOVEN FIBER GLASS. THE CONFORMATIONAL COATING PREFERABLY HAS A DIELECTRIC CONSTANT OF ABOUT 1.5 TO ABOUT 3.5, AND A PERCENT PLANARIZATION OF GREATER THAN ABOUT 3.5%. THE INVENTION ALSO RELATES TO METHODS OF MAKING THE DIELECTRIC COATED CHIP CARRIER.
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公开(公告)号：DE3853453T2
公开(公告)日：1995-10-05
申请号：DE3853453
申请日：1988-08-23
Applicant: IBM
Inventor： ALDRICH GARY ROBERT , MILLIS DAVID BURTON , NOWAK RONALD PETER
Abstract: A method of creating building instructions for a three dimensional cabling assembly for use in a larger assembly. A three dimensional digital computer model of the cabling assembly and a larger assembly is designed ab initio by using a three dimensional mechanical design system. A three dimensional view of the model is then selected and transferred to a two dimensional representation while retaining the aspect ratios of the cabling assembly. Finally, overall lengths of cable sections aligned with the corresponding cable sections themselves are provided in human readable form.
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公开(公告)号：DE3852359T2
公开(公告)日：1995-06-01
申请号：DE3852359
申请日：1988-08-23
Applicant: IBM
Abstract: A method of producing instructions for installing a three dimensional cable assembly in a larger assembly. A three dimensional digital computer model of the cable assembly and a larger assembly is designed ab initio by using a three dimensional mechanical design system. A three dimensional view of the model is then selected and transferred to a two dimensional representation while retaining the aspect ratios of the cable assembly. Finally, the cable assembly geometry is visually distinguished from the larger assembly so that the former assembly is clearly accentuated with respect to the latter.
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公开(公告)号：DE3853453D1
公开(公告)日：1995-05-04
申请号：DE3853453
申请日：1988-08-23
Applicant: IBM
Inventor： ALDRICH GARY ROBERT , MILLIS DAVID BURTON , NOWAK RONALD PETER
Abstract: A method of creating building instructions for a three dimensional cabling assembly for use in a larger assembly. A three dimensional digital computer model of the cabling assembly and a larger assembly is designed ab initio by using a three dimensional mechanical design system. A three dimensional view of the model is then selected and transferred to a two dimensional representation while retaining the aspect ratios of the cabling assembly. Finally, overall lengths of cable sections aligned with the corresponding cable sections themselves are provided in human readable form.
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公开(公告)号：DE3852359D1
公开(公告)日：1995-01-19
申请号：DE3852359
申请日：1988-08-23
Applicant: IBM
Abstract: A method of producing instructions for installing a three dimensional cable assembly in a larger assembly. A three dimensional digital computer model of the cable assembly and a larger assembly is designed ab initio by using a three dimensional mechanical design system. A three dimensional view of the model is then selected and transferred to a two dimensional representation while retaining the aspect ratios of the cable assembly. Finally, the cable assembly geometry is visually distinguished from the larger assembly so that the former assembly is clearly accentuated with respect to the latter.
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