公开(公告)号：JP2008219003A

公开(公告)日：2008-09-18

申请号：JP2008036197

申请日：2008-02-18

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： VOEGELI BENJAMIN T ,  ORNER BRADLEY A ,  FEILCHENFELD NATALIE BARBARA

IPC: H01L21/331 ,  H01L21/8222 ,  H01L21/8248 ,  H01L21/8249 ,  H01L27/06 ,  H01L29/732 ,  H01L29/737

CPC classification number: H01L29/7302 ,  H01L21/8249 ,  H01L27/0623 ,  H01L29/1004 ,  H01L29/66287

Abstract: PROBLEM TO BE SOLVED: To provide a bipolar transistor with a protruberant extrinsic self-aligned base that uses a selective epitaxial growth for BICMOS integration, and to provide a high-performance BiCMOS structure with minimum process complexity, without having to sacrifice the performances of either the bipolar transistors or CMOS devices.
SOLUTION: A high-performance bipolar transistor with a raised extrinsic self-aligned base is integrated into a BiCMOS structure including CMOS devices. By forming pad layers and raising the height of an intrinsic base layer relative to the source and drain of preexisting CMOS devices and by forming an extrinsic base through selective epitaxy, the effect of surface variations is minimized during a lithographic patterning of the extrinsic base. Also, by not employing chemical mechanical planarization process during the fabrication of the bipolar structures, the complexity of process integration is reduced. Internal spacers or external spacers may be formed for isolating the base from the emitter. The pad layers, the intrinsic base layer, and the extrinsic base layer form a mesa structure that coincide with the outer sidewall surfaces.
COPYRIGHT: (C)2008,JPO&INPIT

Abstract translation: 要解决的问题：为了提供具有使用BICMOS集成的选择性外延生长的突出的外部自对准基极的双极晶体管，并且以最小的工艺复杂度提供高性能BiCMOS结构，而不必牺牲 双极晶体管或CMOS器件的性能。

解决方案：具有升高的外部自对准基极的高性能双极晶体管集成到包括CMOS器件的BiCMOS结构中。 通过形成焊盘层并相对于先前存在的CMOS器件的源极和漏极提高本征基极层的高度，并且通过选择性外延形成外部基极，在外部基极的光刻图案化期间，表面变化的影响被最小化。 另外，通过在双极结构的制造过程中不采用化学机械平面化工艺，降低了工艺集成的复杂性。 可以形成内部间隔物或外部隔离物以将基底与发射器隔离。 垫层，本征基层和非本征基层形成与外侧壁表面重合的台面结构。 版权所有（C）2008，JPO＆INPIT

公开(公告)号：MY141640A

公开(公告)日：2010-05-31

申请号：MYPI9706319

申请日：1997-12-26

Applicant: IBM

Inventor： FEILCHENFELD NATALIE BARBARA ,  KRESGE JOHN STEVEN ,  MOORE SCOTT PRESTON ,  NOWAK RONALD PETER ,  WILSON JAMES WARREN

IPC: H01L23/495 ,  H01L21/48 ,  H01L21/60 ,  H01L23/04 ,  H01L23/12 ,  H01L23/14 ,  H01L23/48 ,  H01L23/498 ,  H01L23/52 ,  H05K1/05 ,  H05K3/40 ,  H05K3/46

Abstract: THE PRESENT INVENTION PROVIDES AN ORGANIC CHIP CARRIER (10) PARTICULARLY USEFUL WITH FLIP CHIPS (42), COMPRISING AN ORGANIC DIELECTRIC LAYER (22), A FIRST LAYER OF CIRCUITRY (25) DISPOSED ON THE DIELECTRIC LAYER, AN ORGANIC CONFORMATIONAL COATING (34) DISPOSED OVER THE FIRST LAYER OF DIELECTRIC AND THE FIRST LAYER OF CIRCUITRY, AND A LAYER OF FINE LINE CIRCUITRY (40) HAVING LINE WIDTH OF ABOUT 0. 0508 MM (2.0 MIL) OR LESS. PREFERABLY ABOUT 0.0254 MM (1.0 MIL) OR LESS, PREFERABLY ABOUT 0.01778 MM (0.7 MIL), AND A SPACE BETWEEN LINES OF ABOUT 0.0381 MM (1.5 MIL) OR LESS, PREFERABLY ABOUT 0.02794 MM (1.1 MIL) OR LESS, DISPOSED ON THE CONFORMATIONAL LAYER. PREFERABLY THE DIELECTRIC LAYER IS FREE OF WOVEN FIBER GLASS. THE CONFORMATIONAL COATING PREFERABLY HAS A DIELECTRIC CONSTANT OF ABOUT 1.5 TO ABOUT 3.5, AND A PERCENT PLANARIZATION OF GREATER THAN ABOUT 3.5%. THE INVENTION ALSO RELATES TO METHODS OF MAKING THE DIELECTRIC COATED CHIP CARRIER.

公开(公告)号：DE68925596D1

公开(公告)日：1996-03-21

申请号：DE68925596

申请日：1989-04-25

Applicant: IBM

Inventor： FEILCHENFELD NATALIE BARBARA ,  FUERNISS STEPHEN JOSEPH ,  GLENNING JOHN JOSEPH ,  PAWLOWSKI WALTER PAUL ,  PHELAN GIANA MARRONE ,  RICKERL PAUL GEORGE

IPC: H05K3/06 ,  G03F7/038 ,  G03F7/16 ,  G03F7/32 ,  H01L21/768 ,  H01L23/522 ,  H05K1/03 ,  H05K3/46

Abstract: A polyimide pattern is formed on a substrate by providing a layer of photosensitive polyimide precursor containing the polyimide precursor and a compound having a photosensitive group on the substrate and prebaking the layer. The layer is then exposed imagewise to actinic radiation through a photomask to form an exposed image pattern of the polyimide precursor in the layer. The unexposed areas of the layer are removed using a liquid developer and the exposed image pattern is cured by heating. In one aspect of the present invention, the prebaking step employs a judicious selection of times and temperatures to eliminate the problem of formation of a white residue that occurs from using prior art prebake procedures. In another aspect of the present invention, a particular liquid developer composition is employed to facilitate the formation of sloped vias in the polyimide. In another aspect of the present invention, a particular range of exposure wavelength(s) is employed to obtain smooth walled vias.

公开(公告)号：HK1010605A1

公开(公告)日：1999-06-25

申请号：HK98111590

申请日：1998-10-29

Applicant: IBM

Inventor： FEILCHENFELD NATALIE BARBARA ,  KRESGE JOHN STEVEN ,  MOORE SCOTT PRESTON ,  NOWAK RONALD PETER ,  WILSON JAMES WARREN

IPC: H01L21/48 ,  H01L21/60 ,  H01L23/12 ,  H01L23/14 ,  H01L23/498 ,  H05K1/05 ,  H05K3/40 ,  H05K3/46 ,  H01L ,  H05K

Abstract: The present invention provides an organic chip carrier particularly useful with flip chips. The chip carrier comprises an organic dielectric layer, a first layer of circuitry disposed on the dielectric layer, an organic conformational coating disposed over the first layer of dielectric and the first layer of circuitry, and a layer of fine line circuitry. The fine line circuitry has a line width of about 2.0 mil or less, preferably about 1.0 mil or less, and more preferably about 0.7 mil, and a space between lines of about 1.5 mil or less, preferably about 1.1 mil or less. Preferably the dielectric layer is free of woven fiber glass. The conformational coating preferably has a dielectric constant of about 1.5 to about 3.5, and a percent planarization of greater than about 30%. The invention also relates to methods of making the dielectric coated chip carrier.

公开(公告)号：SG60177A1

公开(公告)日：1999-02-22

申请号：SG1997004679

申请日：1997-12-24

Applicant: IBM

Inventor： FEILCHENFELD NATALIE BARBARA ,  KRESGE JOHN STEVEN ,  MOORE SCOTT PRESTON ,  NOWAK RONALD PETER ,  WILSON JAMES WARREN

IPC: H01L21/48 ,  H01L21/60 ,  H01L23/12 ,  H01L23/14 ,  H01L23/498 ,  H05K1/05 ,  H05K3/40 ,  H05K3/46 ,  H05K1/18

Abstract: The present invention provides an organic chip carrier particularly useful with flip chips. The chip carrier comprises an organic dielectric layer, a first layer of circuitry disposed on the dielectric layer, an organic conformational coating disposed over the first layer of dielectric and the first layer of circuitry, and a layer of fine line circuitry. The fine line circuitry has a line width of about 2.0 mil or less, preferably about 1.0 mil or less, and more preferably about 0.7 mil, and a space between lines of about 1.5 mil or less, preferably about 1.1 mil or less. Preferably the dielectric layer is free of woven fiber glass. The conformational coating preferably has a dielectric constant of about 1.5 to about 3.5, and a percent planarization of greater than about 30%. The invention also relates to methods of making the dielectric coated chip carrier.