公开(公告)号：JPH1056101A

公开(公告)日：1998-02-24

申请号：JP12703097

申请日：1997-05-16

Applicant: IBM

Inventor： WILSON JAMES WARREN

IPC: H01L23/12 ,  H01L21/48 ,  H01L21/60 ,  H01L23/14 ,  H01L23/31 ,  H01L23/498

Abstract: PROBLEM TO BE SOLVED: To provide a method for packaging an electronic device such as an integrated circuit using a ball grid array which does not need mutual connection among through holes or vias and to provide an apparatus for packaging an electronic device. SOLUTION: An electronic device package 10 includes a substrate 12 having an opening 26. A single layer conductive circuit 18 is vacuum evaporated on a first surface 14 of the substrate 12. A thermal conductive element 28 is fixed on a second surface 16. An electronic device 30 is fixed on the thermal conductive element 28 so that it may be placed in the opening of the substrate 12. The electronic device 30 is electrically coupled to a wire bond pad 22 on the first surface 14 of the substrate 12.

公开(公告)号：DE69418395D1

公开(公告)日：1999-06-17

申请号：DE69418395

申请日：1994-07-07

Applicant: IBM

Inventor： CHASE ALAN WALTER ,  WILSON JAMES WARREN

IPC: C08L75/00 ,  H01L21/56 ,  C08L75/04 ,  H01L23/29 ,  H01L23/31

Abstract: A chip carrier is disclosed which includes a chip carrier substrate and at least one semiconductor chip mounted in a flip chip configuration, via solder balls, on a circuitized surface of the chip carrier substrate. The solder balls are encapsulated in a first encapsulant having a composition which includes an epoxy. In addition, at least a portion of the circuitry on the circuitized surface is encapsulated in a second encapsulant having a composition which includes a urethane, and which composition is chosen so that the second encapsulant exhibits a modulus of elasticity which is equal to or less than about 10,000 psi. As a consequence, the second encapsulant exhibits neither internal cracks, nor interfacial cracks at the interface with the first encapsulant, nor does the second encapsulant delaminate from the circuitized surface, when the chip carrier is thermally cycled.

公开(公告)号：HU9701377A2

公开(公告)日：1998-08-28

申请号：HU9701377

申请日：1997-08-11

Applicant: IBM

Inventor： MACQUARRIE STEPHEN WESLEY ,  STORR WAYNE RUSSEL ,  WILSON JAMES WARREN

IPC: H01L21/60 ,  H01L21/58 ,  H01L21/70 ,  H01L23/00 ,  H01L23/053 ,  H01L23/12 ,  H01L23/14 ,  H01L23/28 ,  H01L23/32 ,  H01L23/36 ,  H01L23/495 ,  H01L27/00 ,  H01L27/12

Abstract: A PACKAGE FOR MOUNTING AN INTEGRATED CIRCUIT CHIP (30, 52) TO A CIRCUIT BOARD (48) OR THE LIKE IS PROVIDED. THE PACKAGE INCLUDES A CHIP CARRIER (10) WHICH HAS A METAL SUBSTRATE (12) INCLUDING FIRST AND SECOND OPPOSED FACES. A DIELECTRIC COATING (20) IS PROVIDED ON AT LEAST ONE OF THE FACES, WHICH PREFERABLY IS LESS THAN ABOUT 20 MICRONS IN THICKNESS, AND PREFERABLY HAS A DIELECTRIC CONSTANT FROM ABOUT 35 TO ABOUT 4.0. ELECTRICAL CIRCUITRY IS DISPOSED ON THE DIELECTRIC COATING, SAID CIRCUITRY INCLUDING CHIP MOUNTING PADS (22), CONNECTION PADS (24) AND CIRCUIT TRACES (26) CONNECTING THE CHIP MOUNTING PADS TO THE CONNECTION PADS. AN IC CHIP IS MOUNTED BY FLIP CHIP OR WIRE BONDING OR ADHESIVE CONNECTION ON THE FACE OF THE METAL SUBSTRATE WHICH HAS THE DIELECTRIC COATING THEREON. IN ANY CASE, THE IC CHIP IS ELECTRICALLY CONNECTED TO THE CHIP MOUNTING PADS EITHER BY THE SOLDER BALL (54) OR WIRE BOND (36) CONNECTIONS. ELECTRICAL LEADS (38, 60) EXTEND FROM THE CONNECTION PADS ON THE CHIP CARRIER AND ARE CONNECTED TO CORRESPONDING PADS ON A CIRCUIT BOARD OR THE LIKE TO PROVIDE I/O SIGNALS FOR THE IC CHIP. IN CERTAIN EMBODIMENTS, ADDITIONAL HEAT SINKS (62) CAN BE ATTACHED TO THE CHIP CARRIER AND, ALSO IN CERTAIN EMBODIMENTS, CHIPS CAN BE MOUNTED ON BOTH SIDES OF THE CHIP CARRIER TO INCREASE THE CAPACITY OF THE CHIP CARRIER. (FIG. 1)

公开(公告)号：ES2092216T3

公开(公告)日：1996-11-16

申请号：ES93201907

申请日：1993-07-01

Applicant: IBM

Inventor： FREY BRENDA DIANE ,  JOSEPH CHARLES ARNOLD ,  OLSHEFSKI FRANCIS JOHN ,  WILSON JAMES WARREN

IPC: H01L21/56 ,  H01L21/60 ,  H01L23/12 ,  H01L21/52 ,  H01L23/28 ,  H01L23/29 ,  H01L23/31 ,  H01L23/50 ,  H01L21/58

Abstract: A chip carrier is disclosed which includes a chip carrier substrate and at least one semiconductor chip mounted in a flip chip configuration, via solder balls, on a circuitized surface of the chip carrier substrate. The solder balls are encapsulated in a first encapsulant having a composition which includes an epoxy. In addition, at least a portion of the circuitry on the circuitized surface is encapsulated in a second encapsulant having a composition which includes a urethane, and which composition is chosen so that the second encapsulant exhibits a modulus of elasticity which is equal to or less than about 69.10 N/m . As a consequence, the second encapsulant exhibits neither internal cracks, nor interfacial cracks at the interface with the first encapsulant, nor does the second encapsulant delaminate from the circuitized surface, when the chip carrier is thermally cycled.

公开(公告)号：DE3575952D1

公开(公告)日：1990-03-15

申请号：DE3575952

申请日：1985-02-22

Applicant: IBM

Inventor： BLACKWELL KIM JOSEPH ,  WHITE JR ,  WILSON JAMES WARREN

IPC: C23C14/34 ,  C23C14/04 ,  C23C14/22 ,  C23C14/35 ,  H01J37/34 ,  H01L21/203 ,  H01L21/285 ,  H05K3/40 ,  C23C14/24 ,  H05K3/18

Abstract: A system for vacuum depositing a material onto a sample (12) having a surface recess, such as a hole or channel, therein. The system includes a vacuum chamber capable of attaining a high vacuum and a vacuum deposition source (134) in the chamber for emitting atoms. An energy source (130) is connected to the vacuum deposition source (134) to initiate emission of the atoms therefrom. A sample (12) having an upper surface disposed in the vacuum chamber opposite the vacuum deposition source (134) is adapted to receive the atoms emitted from the vacuum deposition source (134). The ' sample (12) has surface recesses (14-20) therein with walls (22) substantially perpendicular to the plane of the sample (12). Finally, a component (146, 148) for eliminating undesirable depositing angles of atoms is disposed intermediate the vacuum deposition source (134) and the sample (12) in order t to improve the ratio of recess wall to sample surface deposition. Another important feature of the component for eliminating undesirable depositing angles is its ability to reduce heat generated on the sample (12) during the deposition process.

公开(公告)号：MY123948A

公开(公告)日：2006-06-30

申请号：MYPI9804475

申请日：1998-09-30

Applicant: IBM

Inventor： JONES GERARD WALTER ,  KEESLER ROSS WILLIAM ,  MARKOVICH VOYA RISTA ,  RUDIK WILLIAM JOHN ,  WILSON JAMES WARREN ,  WILSON WILLIAM EARL

IPC: H01K3/10 ,  H01L21/48 ,  H05K3/00 ,  H05K3/16 ,  H05K3/38 ,  H05K3/46

Abstract: A PROCESS OF FABRICATING A CIRCUITIZED SUBSTRATE IS PROVIDED WHICH COMPRISING THE STEPS OF: PROVIDING AN ORGANIC SUBSTRATE (12) HAVING CIRCUITRY (14) THEREON; APPLYING A DIELECTRONIC FILM (16, 30) ON THE ORGANIC SUBSTRATE; FORMING MICROVIAS (18) IN SAID DIELECTRIC FILM; SPUTTERING A METAL SEED LAYER (20) ON THE DIELECTRIC FILM AND IN SAID MICROVIAS; PLATING A METALLIC LAYER (22) ON THE METAL SEED LAYER; AND FORMING A CIRCUIT PATTERN THEREON.(FIGURE 1 (E))

公开(公告)号：CZ3498A3

公开(公告)日：1998-11-11

申请号：CZ3498

申请日：1998-01-07

Applicant: IBM

Inventor： MACQUARRIE STEPHEN WESLEY ,  STORR WAYNE ROUSSELL ,  WILSON JAMES WARREN

IPC: H01L21/60 ,  H01L21/58 ,  H01L21/70 ,  H01L23/00 ,  H01L23/053 ,  H01L23/12 ,  H01L23/14 ,  H01L23/28 ,  H01L23/32 ,  H01L23/36 ,  H01L23/495 ,  H01L27/00 ,  H01L27/12

Abstract: A PACKAGE FOR MOUNTING AN INTEGRATED CIRCUIT CHIP (30, 52) TO A CIRCUIT BOARD (48) OR THE LIKE IS PROVIDED. THE PACKAGE INCLUDES A CHIP CARRIER (10) WHICH HAS A METAL SUBSTRATE (12) INCLUDING FIRST AND SECOND OPPOSED FACES. A DIELECTRIC COATING (20) IS PROVIDED ON AT LEAST ONE OF THE FACES, WHICH PREFERABLY IS LESS THAN ABOUT 20 MICRONS IN THICKNESS, AND PREFERABLY HAS A DIELECTRIC CONSTANT FROM ABOUT 35 TO ABOUT 4.0. ELECTRICAL CIRCUITRY IS DISPOSED ON THE DIELECTRIC COATING, SAID CIRCUITRY INCLUDING CHIP MOUNTING PADS (22), CONNECTION PADS (24) AND CIRCUIT TRACES (26) CONNECTING THE CHIP MOUNTING PADS TO THE CONNECTION PADS. AN IC CHIP IS MOUNTED BY FLIP CHIP OR WIRE BONDING OR ADHESIVE CONNECTION ON THE FACE OF THE METAL SUBSTRATE WHICH HAS THE DIELECTRIC COATING THEREON. IN ANY CASE, THE IC CHIP IS ELECTRICALLY CONNECTED TO THE CHIP MOUNTING PADS EITHER BY THE SOLDER BALL (54) OR WIRE BOND (36) CONNECTIONS. ELECTRICAL LEADS (38, 60) EXTEND FROM THE CONNECTION PADS ON THE CHIP CARRIER AND ARE CONNECTED TO CORRESPONDING PADS ON A CIRCUIT BOARD OR THE LIKE TO PROVIDE I/O SIGNALS FOR THE IC CHIP. IN CERTAIN EMBODIMENTS, ADDITIONAL HEAT SINKS (62) CAN BE ATTACHED TO THE CHIP CARRIER AND, ALSO IN CERTAIN EMBODIMENTS, CHIPS CAN BE MOUNTED ON BOTH SIDES OF THE CHIP CARRIER TO INCREASE THE CAPACITY OF THE CHIP CARRIER. (FIG. 1)

公开(公告)号：DE3854792D1

公开(公告)日：1996-02-01

申请号：DE3854792

申请日：1988-02-02

Applicant: IBM

Inventor： SUSKO ROBIN ANNE ,  WILSON JAMES WARREN

IPC: H01L21/302 ,  H01J37/32 ,  H01L21/3065 ,  H01L21/31

公开(公告)号：HK1010605A1

公开(公告)日：1999-06-25

申请号：HK98111590

申请日：1998-10-29

Applicant: IBM

Inventor： FEILCHENFELD NATALIE BARBARA ,  KRESGE JOHN STEVEN ,  MOORE SCOTT PRESTON ,  NOWAK RONALD PETER ,  WILSON JAMES WARREN

IPC: H01L21/48 ,  H01L21/60 ,  H01L23/12 ,  H01L23/14 ,  H01L23/498 ,  H05K1/05 ,  H05K3/40 ,  H05K3/46 ,  H01L ,  H05K

Abstract: The present invention provides an organic chip carrier particularly useful with flip chips. The chip carrier comprises an organic dielectric layer, a first layer of circuitry disposed on the dielectric layer, an organic conformational coating disposed over the first layer of dielectric and the first layer of circuitry, and a layer of fine line circuitry. The fine line circuitry has a line width of about 2.0 mil or less, preferably about 1.0 mil or less, and more preferably about 0.7 mil, and a space between lines of about 1.5 mil or less, preferably about 1.1 mil or less. Preferably the dielectric layer is free of woven fiber glass. The conformational coating preferably has a dielectric constant of about 1.5 to about 3.5, and a percent planarization of greater than about 30%. The invention also relates to methods of making the dielectric coated chip carrier.

公开(公告)号：SG60177A1

公开(公告)日：1999-02-22

申请号：SG1997004679

申请日：1997-12-24

Applicant: IBM

Inventor： FEILCHENFELD NATALIE BARBARA ,  KRESGE JOHN STEVEN ,  MOORE SCOTT PRESTON ,  NOWAK RONALD PETER ,  WILSON JAMES WARREN

IPC: H01L21/48 ,  H01L21/60 ,  H01L23/12 ,  H01L23/14 ,  H01L23/498 ,  H05K1/05 ,  H05K3/40 ,  H05K3/46 ,  H05K1/18

Abstract: The present invention provides an organic chip carrier particularly useful with flip chips. The chip carrier comprises an organic dielectric layer, a first layer of circuitry disposed on the dielectric layer, an organic conformational coating disposed over the first layer of dielectric and the first layer of circuitry, and a layer of fine line circuitry. The fine line circuitry has a line width of about 2.0 mil or less, preferably about 1.0 mil or less, and more preferably about 0.7 mil, and a space between lines of about 1.5 mil or less, preferably about 1.1 mil or less. Preferably the dielectric layer is free of woven fiber glass. The conformational coating preferably has a dielectric constant of about 1.5 to about 3.5, and a percent planarization of greater than about 30%. The invention also relates to methods of making the dielectric coated chip carrier.