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    Carrier frequency phase-readjustment device
    1.
    发明授权
    Carrier frequency phase-readjustment device 失效
    载波频率相位读取装置

    公开(公告)号：US3577082A

    公开(公告)日：1971-05-04

    申请号：US3577082D

    申请日：1969-03-05

    Applicant: IBM

    Inventor： LAUTIER ALEX HONORE ,  NUSSBAUMER HENRI JEAN ,  PIERRET JEAN MARC

    IPC: H04B1/68 ,  H04L27/06 ,  H04B1/16

    CPC classification number: H04B1/68 ,  H04L27/066

    Abstract: A phase synchronizing device for the carrier of a single sideband transmission system. Two pilot frequencies are transmitted with the synchronization signal and are decoded at the receiver to provide a signal indicating the correct phase of the demodulating carrier signal. The transmitted carrier signal controls the frequency of an oscillator and the initial phase of the regenerated carrier signal is set a the start of reception by the decoded pilot signals.

    Method and apparatus for equalizing phase-modulated signals
    2.
    发明授权
    Method and apparatus for equalizing phase-modulated signals 失效
    用于均衡相位调制信号的方法和装置

    公开(公告)号：US3890572A

    公开(公告)日：1975-06-17

    申请号：US43742974

    申请日：1974-01-28

    Applicant: IBM

    Inventor： DESBLANCHE ANDRE EUGENE ,  PIERRET JEAN MARC

    IPC: H04B3/06 ,  H03H15/00 ,  H03H17/00 ,  H03H21/00 ,  H04L27/01 ,  H04L27/22 ,  H04L27/18

    CPC classification number: H04L27/01

    Abstract: A method of equalizing a phase modulated signal and apparatus for doing so without a frequency field transfer are disclosed. The input signals are fed through a variable transfer transversal filter for obtaining an equalized signal; an error adjustment signal is generated by comparing the output from the transversal filter with a reference signal at time instants defined by a clock which generates timing signals at the data bit rate. The transfer function of the transversal filter is then adjusted for minimum error. The method of generating the error signal includes steps of extracting the carrier frequency from the received signal; generating from the extracted carrier frequency n possible reference signals, and selecting from said n reference signals the particular one to be used at a given characteristic instant.

    Abstract translation: 公开了一种均衡相位调制信号的方法和用于不进行频率场传输的装置。 输入信号通过可变传输横向滤波器馈送以获得均衡信号; 通过将来自横向滤波器的输出与由以数据比特率产生定时信号的时钟定义的时刻的参考信号进行比较来产生误差调整信号。 然后调整横向滤波器的传递函数以获​​得最小误差。 产生误差信号的方法包括从接收信号中提取载波频率的步骤; 从所提取的载波频率n产生可能的参考信号，并从所述n个参考信号中选择要在给定特征时刻使用的特定的参考信号。

    4.
    发明专利
    未知

    公开(公告)号：DE2317597A1

    公开(公告)日：1973-11-15

    申请号：DE2317597

    申请日：1973-04-07

    Applicant: IBM

    Inventor： LAUTIER ALEX ,  MADDENS FRANCIS PAUL ,  NUSSBAUMER HENRI JEAN ,  PIERRET JEAN MARC

    IPC: H04B3/06 ,  H03H17/00 ,  H03H17/08 ,  H04L27/01 ,  H04L27/22

    Abstract: A self-adjustable equalizer for a phase modulation communication system in which the equalizer output signal s is sampled at the modulation rate and weighted by a factor proportional to envelope amplitude distortion dR/R, R being the envelope amplitude at given instants and the product sdR/R being the adjustment control signal. In the preferred embodiment the product of the sign of s and the sign of dR serves as the control or error signal. One implementation frequency translates the equalizer output signal and compares the amplitude of the translated signal with a reference at given instants to determine the sign of dR which is eventually multiplied by the sign of s.

    APPARATUS FOR DERIVING CLOCK SIGNALS FROM A DIGITAL DATA PULSE TRAIN
    5.
    发明专利
    APPARATUS FOR DERIVING CLOCK SIGNALS FROM A DIGITAL DATA PULSE TRAIN 未知

    公开(公告)号：GB1276195A

    公开(公告)日：1972-06-01

    申请号：GB4375869

    申请日：1969-09-04

    Applicant: IBM

    Inventor： PIERRET JEAN MARC

    IPC: H03K5/00 ,  H04L7/02

    Abstract: 1276195 Digital data transmission systems INTERNATIONAL BUSINESS MACHINES CORP 4 Sept 1969 [4 Sept 1968] 43758/69 Heading H4P A receiver for deriving clock pulses from a digital data pulse train in which each data item is coded as a main pulse preceded and followed by echo pulses is described. This is for use in a data transmission system as described in Specifications 1,154,648 and 1,271,753. The clock pulses produced are used to modify the timing of sampling clock pulses used on the train via lines 51, 61 and to maintain synchronism with the incoming pulse train. In the embodiment of Fig. 2 the main pulses can have any one of six possible amplitude relationships, taking magnitude and sign into account, with a pulse train element separated therefrom by a predetermined time T/2. The present receiver detects that two pulses have the correct time relationship T/2, one of the correct amplitude relationships listed on Fig. 2 (bottom right hand corner) and that the amplitudes are those unique to main pulses. The pulse train enters a comparator 21 having a first time delay 25 and a second time delay 30 of T/2 which is the predetermined time relationship. Two pulses, normally separated by time T/2 go to six comparison circuits, adders 33 to 38, each of which tests for one amplitude relationship, i.e. circuit 33 tests that pulses A and B have the relationship AB

    7.
    发明专利
    未知

    公开(公告)号：FR1504609A

    公开(公告)日：1967-12-08

    申请号：FR06008054

    申请日：1966-09-21

    Applicant: IBM FRANCE

    Inventor： PIERRET JEAN MARC

    IPC: H04L25/48 ,  H04L25/497

    Abstract: 1,154,648. Digital transmission systems. INTERNATIONAL BUSINESS MACHINES CORP. 5 Sept., 1967 [21 Sept., 1966], No. 40619/67. Heading H4P. Each bit of data to be transmitted is encoded as a main pulse followed and preceded by several "echo" pulses of lower amplitude than the main pulse, the encoding being such that no main pulse coincides with any echo pulse. In the system described each input bit of duration T, Fig. 2 (part shown), produces a main pulse A of duration T/2, two echo pulses a1, a 1 1 of opposite polarity to pulse A, and two smaller echoes a3, a 1 3 of the same polarity, the echo pulses being spaced as shown and having a duration T/2. An input bit of opposite state produces the inverse signal. The transmitted signal is the sum of the encoded bits. The encoder, Fig. 3a (not shown), comprises a shift register fed by the input bits and giving a parallel output. The final stage of the register controls a switched potential divider which passes a pulse representing the main pulse to a first gate. The echo pulses appear at the output of a second gate, one input of which is obtained from a potential divider fed by the outputs of switched dividers controlled by other stages of the register. The gates are enabled alternately for a period T which is 90 degrees out of phase with the input bits. Thus the gates respectively pass two main pulses or two echo pulses when enabled. The gates' outputs pass via an OR gate to the transmitter. At the receiver the original data is recovered by sampling the received signal at times 2nT and 2nt + T/2.

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