公开(公告)号：EP1754253A4

公开(公告)日：2008-10-22

申请号：EP05736453

申请日：2005-04-06

Applicant: IBM

Inventor： GEISS PETER J ,  JOSEPH ALVIN J ,  LIU QZHI ,  ORNER BRADLEY A

IPC: H01L21/331 ,  H01L21/8249 ,  H01L27/06 ,  H01L29/10

CPC classification number: H01L29/0804 ,  H01L21/8249 ,  H01L27/0623 ,  H01L29/1004 ,  H01L29/66287

Abstract: Disclosed is a bipolar complementary metal oxide semiconductor (BiCMOS) or NPN/PNP device that has a collector (112), an intrinsic base (118) above the collector, shallow trench isolation regions (114) adjacent the collector, a raised extrinsic base (202) above the intrinsic base, a T-shaped emitter (800) above the extrinsic base, spacers (700) adjacent the emitter, and a silicide (400) layer that is separated from the emitter by the spacers.

公开(公告)号：JP2008219003A

公开(公告)日：2008-09-18

申请号：JP2008036197

申请日：2008-02-18

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： VOEGELI BENJAMIN T ,  ORNER BRADLEY A ,  FEILCHENFELD NATALIE BARBARA

IPC: H01L21/331 ,  H01L21/8222 ,  H01L21/8248 ,  H01L21/8249 ,  H01L27/06 ,  H01L29/732 ,  H01L29/737

CPC classification number: H01L29/7302 ,  H01L21/8249 ,  H01L27/0623 ,  H01L29/1004 ,  H01L29/66287

Abstract: PROBLEM TO BE SOLVED: To provide a bipolar transistor with a protruberant extrinsic self-aligned base that uses a selective epitaxial growth for BICMOS integration, and to provide a high-performance BiCMOS structure with minimum process complexity, without having to sacrifice the performances of either the bipolar transistors or CMOS devices.
SOLUTION: A high-performance bipolar transistor with a raised extrinsic self-aligned base is integrated into a BiCMOS structure including CMOS devices. By forming pad layers and raising the height of an intrinsic base layer relative to the source and drain of preexisting CMOS devices and by forming an extrinsic base through selective epitaxy, the effect of surface variations is minimized during a lithographic patterning of the extrinsic base. Also, by not employing chemical mechanical planarization process during the fabrication of the bipolar structures, the complexity of process integration is reduced. Internal spacers or external spacers may be formed for isolating the base from the emitter. The pad layers, the intrinsic base layer, and the extrinsic base layer form a mesa structure that coincide with the outer sidewall surfaces.
COPYRIGHT: (C)2008,JPO&INPIT

Abstract translation: 要解决的问题：为了提供具有使用BICMOS集成的选择性外延生长的突出的外部自对准基极的双极晶体管，并且以最小的工艺复杂度提供高性能BiCMOS结构，而不必牺牲 双极晶体管或CMOS器件的性能。

解决方案：具有升高的外部自对准基极的高性能双极晶体管集成到包括CMOS器件的BiCMOS结构中。 通过形成焊盘层并相对于先前存在的CMOS器件的源极和漏极提高本征基极层的高度，并且通过选择性外延形成外部基极，在外部基极的光刻图案化期间，表面变化的影响被最小化。 另外，通过在双极结构的制造过程中不采用化学机械平面化工艺，降低了工艺集成的复杂性。 可以形成内部间隔物或外部隔离物以将基底与发射器隔离。 垫层，本征基层和非本征基层形成与外侧壁表面重合的台面结构。 版权所有（C）2008，JPO＆INPIT

公开(公告)号：WO2005104680A3

公开(公告)日：2007-07-05

申请号：PCT/US2005011711

申请日：2005-04-06

Applicant: IBM ,  GEISS PETER J ,  JOSEPH ALVIN J ,  LIU QZHI ,  ORNER BRADLEY A

Inventor： GEISS PETER J ,  JOSEPH ALVIN J ,  LIU QZHI ,  ORNER BRADLEY A

IPC: H01L31/072 ,  H01L21/331 ,  H01L21/8249 ,  H01L27/06 ,  H01L29/10

CPC classification number: H01L29/0804 ,  H01L21/8249 ,  H01L27/0623 ,  H01L29/1004 ,  H01L29/66287

Abstract: Disclosed is a bipolar complementary metal oxide semiconductor (BiCMOS) or NPN/PNP device that has a collector (112), an intrinsic base (118) above the collector, shallow trench isolation regions (114) adjacent the collector, a raised extrinsic base (202) above the intrinsic base, a T-shaped emitter (800) above the extrinsic base, spacers (700) adjacent the emitter, and a silicide (400) layer that is separated from the emitter by the spacers.

Abstract translation: 公开了一种双极互补金属氧化物半导体（BiCMOS）或NPN / PNP器件，其具有集电极（112），集电极上方的本征基极（118），与集电极相邻的浅沟槽隔离区域（114），凸起的外部基极 202），在外部基极之上的T形发射极（800），与发射极相邻的间隔物（700）以及通过间隔物与发射极分离的硅化物（400）层。