公开(公告)号：EP1794806A4

公开(公告)日：2011-06-29

申请号：EP05798479

申请日：2005-09-20

Applicant: IBM

Inventor： GEISS PETER J ,  GRAY PETER B ,  JOSEPH ALVIN J ,  LIU QIZHI

IPC: H01L31/072

CPC classification number: H01L29/0821 ,  H01L21/8249 ,  H01L27/0623 ,  H01L29/66242 ,  H01L29/66318

公开(公告)号：EP1754253A4

公开(公告)日：2008-10-22

申请号：EP05736453

申请日：2005-04-06

Applicant: IBM

Inventor： GEISS PETER J ,  JOSEPH ALVIN J ,  LIU QZHI ,  ORNER BRADLEY A

IPC: H01L21/331 ,  H01L21/8249 ,  H01L27/06 ,  H01L29/10

CPC classification number: H01L29/0804 ,  H01L21/8249 ,  H01L27/0623 ,  H01L29/1004 ,  H01L29/66287

Abstract: Disclosed is a bipolar complementary metal oxide semiconductor (BiCMOS) or NPN/PNP device that has a collector (112), an intrinsic base (118) above the collector, shallow trench isolation regions (114) adjacent the collector, a raised extrinsic base (202) above the intrinsic base, a T-shaped emitter (800) above the extrinsic base, spacers (700) adjacent the emitter, and a silicide (400) layer that is separated from the emitter by the spacers.

公开(公告)号：JP2003347233A

公开(公告)日：2003-12-05

申请号：JP2003132210

申请日：2003-05-09

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーション

Inventor： GEISS PETER J ,  JOSEPH R GRECO ,  KONTRA RICHARD S ,  LANNING EMILY

IPC: H01L21/28 ,  H01L21/20 ,  H01L21/265 ,  H01L21/331 ,  H01L21/822 ,  H01L27/04 ,  H01L29/08 ,  H01L29/49 ,  H01L29/732 ,  H01L29/78

CPC classification number: H01L29/6656 ,  H01L21/02381 ,  H01L21/02488 ,  H01L21/02532 ,  H01L21/02595 ,  H01L21/0262 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/2652 ,  H01L29/0804 ,  H01L29/1083 ,  H01L29/4916 ,  H01L29/4925 ,  H01L29/66242 ,  H01L29/7375 ,  H01L29/7378 ,  Y10S257/914

Abstract: PROBLEM TO BE SOLVED: To provide a method of adjusting a particle size in a polysilicon layer, and to provide a device manufactured by the method.
SOLUTION: In the method, the polysilicon layer is formed on a substrate and the particle size in the polysilicon layer is adjusted so that the average resulting particle size of the polysilicon layer after a polysilicon particle-size adjusting ion is injected into the layer and prescribed annealing is performed on the layer becomes higher or lower than an average resulting particle-size that must be obtained after the same annealing is performed on the polysilicon layer without injecting the ion into the layer by injecting the particle-size adjusting ion into the polysilicon layer.
COPYRIGHT: (C)2004,JPO

Abstract translation: 要解决的问题：提供一种调整多晶硅层中的粒径的方法，并提供通过该方法制造的器件。 解决方案：在该方法中，在衬底上形成多晶硅层，并调节多晶硅层中的粒径，使多晶硅粒度调整离子后的多晶硅层的平均粒径注入到 在层上进行规定的退火，高于或低于在多晶硅层上进行相同的退火之后必须获得的平均粒子尺寸，而不通过将粒径调节离子注入到层中而将离子注入层中 多晶硅层。 版权所有（C）2004，JPO

公开(公告)号：JP2005260239A

公开(公告)日：2005-09-22

申请号：JP2005066770

申请日：2005-03-10

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： GEISS PETER J ,  MARWAN H KHATER ,  LIU QIZHI ,  RANDY W MANN ,  PURTELL ROBERT J ,  BETHANN RAINEY ,  JAE-SUNG RIEH ,  STRICKER ANDREAS D

IPC: H01L21/28 ,  H01L21/331 ,  H01L21/8222 ,  H01L21/8248 ,  H01L21/8249 ,  H01L27/06 ,  H01L29/417 ,  H01L29/73 ,  H01L29/732 ,  H01L29/737 ,  H01L31/072 ,  H01L31/109

CPC classification number: H01L29/66242 ,  H01L21/28518 ,  H01L21/8249 ,  H01L27/0623 ,  H01L29/0804 ,  H01L29/456 ,  H01L29/7371

Abstract: PROBLEM TO BE SOLVED: To provide a method for manufacturing a hetero-junction bipolar transistor having a raised base of which the base resistance is decreased by forming silicide extending to an emitter region in a self-aligning manner on a raised base.
SOLUTION: This silicide formation is incorporated in a BiCMOS process flow after forming a raised and extrinsic base. The bipolar transistor has the raised and extrinsic base, and the hetero-junction bipolar transistor has silicide positioned on the raised and extrinsic base. The silicide on the extrinsic base extends to an emitter in a self-aligning manner. The emitter is isolated from the silicide by a spacer.
COPYRIGHT: (C)2005,JPO&NCIPI

Abstract translation: 要解决的问题：提供一种通过在自升高的基极上以自对准的方式形成延伸到发射极区域的硅化物来提供具有升高的基极的异质结双极晶体管的方法，其中基极电阻降低。 解决方案：该硅化物形成在形成凸起和外在基体之后并入BiCMOS工艺流程中。 双极晶体管具有凸起和非本征基极，并且异质结双极晶体管具有位于升高和外部基极上的硅化物。 外在基极上的硅化物以自对准方式延伸到发射极。 发射极通过间隔物与硅化物隔离。 版权所有（C）2005，JPO＆NCIPI

公开(公告)号：WO2006034355A2

公开(公告)日：2006-03-30

申请号：PCT/US2005033851

申请日：2005-09-20

Applicant: IBM ,  GEISS PETER J ,  GRAY PETER B ,  JOSEPH ALVIN J ,  LIU QIZHI

Inventor： GEISS PETER J ,  GRAY PETER B ,  JOSEPH ALVIN J ,  LIU QIZHI

IPC: H01L31/109

CPC classification number: H01L29/0821 ,  H01L21/8249 ,  H01L27/0623 ,  H01L29/66242 ,  H01L29/66318

Abstract: A heterobipolar transistor (HBT) for high-speed BiCMOS applications is provided in which the collector resistance, Rc, is lowered by providing a buried refractory metal silicide layer underneath the shallow trench isolation region on the subcollector of the device. Specifically, the HBT of the present invention includes a substrate (12) including at least a subcollector (13); a buried refractory metal silicide layer (28) located on the subcollector; and a shallow trench isolation region (30) located on a surface of the buried refractory metal silicide layer. The present invention also provides a method of fabricating such a HBT. The method includes forming a buried refractory metal silicide underneath the shallow trench isolation region on the subcollector of the device.

Abstract translation: 提供了用于高速BiCMOS应用的异步双极晶体管（HBT），其中通过在器件的子集电极上的浅沟槽隔离区域的下面提供掩埋难熔金属硅化物层来降低集电极电阻Rc。 具体地，本发明的HBT包括至少包括子集电极（13）的基板（12）。 位于子集电极上的埋置难熔金属硅化物层（28）; 以及位于所述埋入难熔金属硅化物层的表面上的浅沟槽隔离区域（30）。 本发明还提供一种制造这种HBT的方法。 该方法包括在器件的子集电极上的浅沟槽隔离区域的下面形成埋置难熔金属硅化物。

公开(公告)号：WO2005104680A3

公开(公告)日：2007-07-05

申请号：PCT/US2005011711

申请日：2005-04-06

Applicant: IBM ,  GEISS PETER J ,  JOSEPH ALVIN J ,  LIU QZHI ,  ORNER BRADLEY A

Inventor： GEISS PETER J ,  JOSEPH ALVIN J ,  LIU QZHI ,  ORNER BRADLEY A

IPC: H01L31/072 ,  H01L21/331 ,  H01L21/8249 ,  H01L27/06 ,  H01L29/10

CPC classification number: H01L29/0804 ,  H01L21/8249 ,  H01L27/0623 ,  H01L29/1004 ,  H01L29/66287

Abstract: Disclosed is a bipolar complementary metal oxide semiconductor (BiCMOS) or NPN/PNP device that has a collector (112), an intrinsic base (118) above the collector, shallow trench isolation regions (114) adjacent the collector, a raised extrinsic base (202) above the intrinsic base, a T-shaped emitter (800) above the extrinsic base, spacers (700) adjacent the emitter, and a silicide (400) layer that is separated from the emitter by the spacers.

Abstract translation: 公开了一种双极互补金属氧化物半导体（BiCMOS）或NPN / PNP器件，其具有集电极（112），集电极上方的本征基极（118），与集电极相邻的浅沟槽隔离区域（114），凸起的外部基极 202），在外部基极之上的T形发射极（800），与发射极相邻的间隔物（700）以及通过间隔物与发射极分离的硅化物（400）层。

公开(公告)号：GB2362508B

公开(公告)日：2004-02-11

申请号：GB0027232

申请日：2000-11-07

Applicant: IBM

Inventor： COOLBAUGH DOUGLAS D ,  DUNN JAMES S ,  GEISS PETER J ,  GRAY PETER B ,  HARAME DAVID L ,  SCHONENBERG KATHRYN T ,  ST ONGE STEPHEN A ,  SUBBANNA SESHADRI

IPC: H01L21/328 ,  H01L21/762 ,  H01L21/763 ,  H01L21/8222 ,  H01L21/8248 ,  H01L21/8249 ,  H01L27/06

Abstract: A method of forming a BiCMOS integrated circuit is provided which comprises the steps of: (a) forming a first portion of a bipolar device in first regions of a substrate; (b) forming a first protective layer over said first regions to protect said first portion of said bipolar devices; (c) forming field effect transistor devices in second regions of said substrate; (d) forming a second protective layer over said second regions of said substrate to protect said field effect transistor devices; (e) removing said first protective layer; (f) forming a second portion of said bipolar devices in said first regions of said substrate; and (g) removing said second protective layer.

公开(公告)号：GB2362508A

公开(公告)日：2001-11-21

申请号：GB0027232

申请日：2000-11-07

Applicant: IBM

Inventor： COOLBAUGH DOUGLAS D ,  DUNN JAMES S ,  GEISS PETER J ,  GRAY PETER B ,  HARAME DAVID L ,  SCHONENBERG KATHRYN T ,  ST ONGE STEPHEN A ,  SUBBANNA SESHADRI

IPC: H01L21/328 ,  H01L21/762 ,  H01L21/763 ,  H01L21/8222 ,  H01L21/8248 ,  H01L21/8249 ,  H01L27/06

Abstract: A method of forming a semiconductor integrated circuit such as a BiCMOS integrated circuit comprises the steps of: (a) forming a first portion of a bipolar device in a first region of a substrate; (b) forming a first protective layer over the first region to protect the first portion of the bipolar devices; (c) forming field effect transistor devices in second regions of the substrate; (d) forming a second protective layer over the second regions of the substrate to protect the field effect transistor devices; (e) removing the first protective layer; (f) forming a second portion of the bipolar devices in the first region of the substrate; and (g) removing the second protective layer.