公开(公告)号：GB2524003A

公开(公告)日：2015-09-16

申请号：GB201404173

申请日：2014-03-10

Applicant: IBM

Inventor： ANTONAKOPOULOS THEODORE ,  ELEFTHERIOU EVANGELOS STAVROS ,  KOLTSIDAS IOANNIS ,  MUELLER PETER ,  PALLI ASPASIA ,  PLETKA ROMAN

IPC: G11C13/00 ,  G06F11/10 ,  G06F12/00 ,  G11C11/56 ,  H01L45/00

Abstract: A storage device 100 and method of operation (figure 5), comprising a channel controller 10 and phase change memory integrated circuits 20, (PCM ICs) arranged in sub-channels 30, wherein each of the sub-channels 30 comprises several PCM ICs connected by at least one data bus line 35, in which at least one data bus line connects to the channel controller which is configured to write data to and/or read data from the PCM ICs according to a matrix configuration of PCM ICs. The number of columns of this matrix configuration respectively corresponds to a number Ns of the sub-channels, Ns ≥ 2, the sub-channels 30 forming a channel; and a number of rows of this matrix configuration respectively corresponds to a number Nl of sub-banks (40), Nl ≥ 2, the sub-banks 40 forming a bank, wherein each of the sub-banks 40 comprises PCM ICs that belong, each, to a distinct sub-channel 30. The channel controller is configured to break data (71,72 figure 2) to be written to the PCM ICs into data chunks (711-71n, 721-72n figure 2) and buffer data chunks according to the data bus lines 35 consistent with the organisation of the sub banks. Thus the asymmetry in the write/read times associated with PCM memories is mitigated.