公开(公告)号：AT479986T

公开(公告)日：2010-09-15

申请号：AT03732870

申请日：2003-06-13

Applicant: IBM

Inventor： ANTONAKOPOULOS THEODORE ,  ELEFTHERIOU EVANGELOS ,  POZIDIS HARIS

IPC: G11B20/12 ,  G11B20/14 ,  G11B9/14 ,  G11B20/10 ,  G11B27/30 ,  H03M5/14

Abstract: A method and apparatus for overwriting data in a probe-based data storage device wherein data is represented by the presence and absence of pits formed in a storage surface by a probe of the device is provided. Input data is first coded such that successive bits of a given value x in the coded input data (b0, b1, b2, . . . ,) are separated by at least d bits of the complementary value {tilde over (x)}, where d is a predetermined number>=2. Overwrite data bits (v0, v1, v2, . . . ,) are then generated by encoding the coded input data bits (b0, b1, b2, . . . ,).

公开(公告)号：GB2524003A

公开(公告)日：2015-09-16

申请号：GB201404173

申请日：2014-03-10

Applicant: IBM

Inventor： ANTONAKOPOULOS THEODORE ,  ELEFTHERIOU EVANGELOS STAVROS ,  KOLTSIDAS IOANNIS ,  MUELLER PETER ,  PALLI ASPASIA ,  PLETKA ROMAN

IPC: G11C13/00 ,  G06F11/10 ,  G06F12/00 ,  G11C11/56 ,  H01L45/00

Abstract: A storage device 100 and method of operation (figure 5), comprising a channel controller 10 and phase change memory integrated circuits 20, (PCM ICs) arranged in sub-channels 30, wherein each of the sub-channels 30 comprises several PCM ICs connected by at least one data bus line 35, in which at least one data bus line connects to the channel controller which is configured to write data to and/or read data from the PCM ICs according to a matrix configuration of PCM ICs. The number of columns of this matrix configuration respectively corresponds to a number Ns of the sub-channels, Ns ≥ 2, the sub-channels 30 forming a channel; and a number of rows of this matrix configuration respectively corresponds to a number Nl of sub-banks (40), Nl ≥ 2, the sub-banks 40 forming a bank, wherein each of the sub-banks 40 comprises PCM ICs that belong, each, to a distinct sub-channel 30. The channel controller is configured to break data (71,72 figure 2) to be written to the PCM ICs into data chunks (711-71n, 721-72n figure 2) and buffer data chunks according to the data bus lines 35 consistent with the organisation of the sub banks. Thus the asymmetry in the write/read times associated with PCM memories is mitigated.

公开(公告)号：GB2520708A

公开(公告)日：2015-06-03

申请号：GB201320982

申请日：2013-11-28

Applicant: IBM

Inventor： ANTONAKOPOULOS THEODORE ,  MITTELHOLZER THOMAS ,  PAPANDREOU NIKOLAOS ,  POZIDIS CHARALAMPOS

IPC: G11C11/56 ,  G06F11/10 ,  G11C13/00

Abstract: A multi-stage codeword detector 100 and method of operation for detecting codewords from read signals RS received from a multi-level memory device 200. The multi-stage codeword detector 100 includes a first detection stage 110 for a coarse detection of a first codeword C1 from a received read signal RS, a second detection stage 120 for a fine detection of a second codeword C2 from the received read signal RS, and a deciding entity 130 for deciding on using the second detection stage 120 for the received read signal RS in dependence on a reliability indicator RI indicating a certain reliability level of the received read signal RS. The deciding entity may be configured to forward the first codeword C1 after decoding to an output buffer (150 figure 5) if the reliability indicator RI indicated that the reliability level of the RS is higher than a reliability threshold, and to forward the RS to the second detection stage 130 if the reliability indicator indicates the reliability level is less than or equal to a certain reliability threshold. The reliability indicator may include information based on the noise level or error rate of the received signal RS or may be based on temperature or number of set/reset cycles of the memory cells. Preferably a coarse codeword detection unit may be incorporated based on a vector based minimum distance criterion providing a coarse estimated level means (CM) of RS. Similarly a vector based fine level estimation means (FM) is associated with the second codeword. The multi-level memory devise may be a phase change memory device MLC PCM or a MLC Flash device.

公开(公告)号：DE60334000D1

公开(公告)日：2010-10-14

申请号：DE60334000

申请日：2003-06-13

Applicant: IBM

Inventor： ANTONAKOPOULOS THEODORE ,  ELEFTHERIOU EVANGELOS S ,  POZIDIS HARIS

IPC: G11B20/12 ,  G11B20/14 ,  G11B9/14 ,  G11B20/10 ,  G11B27/30 ,  H03M5/14

公开(公告)号：AU2003239297A1

公开(公告)日：2004-01-19

申请号：AU2003239297

申请日：2003-06-13

Applicant: IBM

Inventor： ANTONAKOPOULOS THEODORE ,  ELEFTHERIOU EVANGELOS S ,  POZIDIS HARIS

IPC: G11B20/14 ,  G11B9/14 ,  G11B20/10 ,  G11B20/12 ,  G11B27/30 ,  H03M5/14

Abstract: A method and apparatus for overwriting data in a probe-based data storage device wherein data is represented by the presence and absence of pits formed in a storage surface by a probe of the device is provided. Input data is first coded such that successive bits of a given value x in the coded input data (b0, b1, b2, . . . ,) are separated by at least d bits of the complementary value {tilde over (x)}, where d is a predetermined number>=2. Overwrite data bits (v0, v1, v2, . . . ,) are then generated by encoding the coded input data bits (b0, b1, b2, . . . ,).