公开(公告)号：GB2579533A

公开(公告)日：2020-06-24

申请号：GB202005675

申请日：2018-10-16

Applicant: IBM

Inventor： KANGGUO CHENG ,  JUNTAO LI ,  CHOONGHYUN LEE ,  PENG XU

IPC: H01L21/336 ,  H01L21/8238 ,  H01L27/092

Abstract: Semiconductor devices and methods for making the same include patterning a stack of layers that includes channel layers, first sacrificial layers between the channel layers, and second sacrificial layers between the channel layers and the first sacrificial layers, to form one or more device regions. The first sacrificial layers are formed from a material that has a same lattice constant as a material of the first sacrificial layers and the second sacrificial layers are formed from a material that has a lattice mismatch with the material of the first sacrificial layers. Source and drain regions are formed from sidewalls of the channel layers in the one or more device regions. The first and second sacrificial layers are etched away to leave the channel layers suspended from the source and drain regions. A gate stack is deposited on the channel layers.

公开(公告)号：GB2579533B

公开(公告)日：2020-11-04

申请号：GB202005675

申请日：2018-10-16

Applicant: IBM

Inventor： KANGGUO CHENG ,  JUNTAO LI ,  CHOONGHYUN LEE ,  PENG XU

IPC: H01L21/336 ,  H01L21/8238 ,  H01L27/092

Abstract: Integrated chips include vertically stacked channel layers, with a first stack in a first device region and a second stack in a second device region. A first dielectric layer is formed conformally on the vertically stacked channel layers in the first device region. A second dielectric layer is formed conformally on the vertically stacked channel layers in the second device region. Gate conductors are formed around the vertically stacked channel layers in both the first device region and the second device region, filling a space between surfaces of the respective first dielectric layer and second dielectric layer.