公开(公告)号：GB2594428B

公开(公告)日：2022-03-16

申请号：GB202112164

申请日：2020-01-28

Applicant: IBM

Inventor： CHOONGHYUN LEE ,  TAKASHI ANDO ,  ALEXANDER REZNICEK ,  JINGYUN ZHANG ,  POUYA HASHEMI

IPC: H01L45/00 ,  G11C13/00 ,  H01L21/335 ,  H01L27/24 ,  H01L29/66 ,  H01L29/78

Abstract: A resistive memory structure is provided. The resistive memory structure includes a vertical fin on a substrate, wherein the sidewalls of the vertical fin each have a {100} crystal face. The resistive memory structure further includes a fin template on the vertical fin, and a gate structure on the vertical fin. The resistive memory structure further includes a top source/drain on opposite sidewalls of the vertical fin, and a bottom electrode layer on the top source/drain, wherein the bottom electrode layer is on opposite sides of the fin template. The resistive memory structure further includes a first middle resistive layer on a portion of the bottom electrode layer, a top electrode layer on the first middle resistive layer, and a first electrical contact on a portion of the bottom electrode layer.

公开(公告)号：GB2579533B

公开(公告)日：2020-11-04

申请号：GB202005675

申请日：2018-10-16

Applicant: IBM

Inventor： KANGGUO CHENG ,  JUNTAO LI ,  CHOONGHYUN LEE ,  PENG XU

IPC: H01L21/336 ,  H01L21/8238 ,  H01L27/092

Abstract: Integrated chips include vertically stacked channel layers, with a first stack in a first device region and a second stack in a second device region. A first dielectric layer is formed conformally on the vertically stacked channel layers in the first device region. A second dielectric layer is formed conformally on the vertically stacked channel layers in the second device region. Gate conductors are formed around the vertically stacked channel layers in both the first device region and the second device region, filling a space between surfaces of the respective first dielectric layer and second dielectric layer.

公开(公告)号：GB2581116B

公开(公告)日：2021-03-03

申请号：GB202008885

申请日：2018-12-14

Applicant: IBM

Inventor： CHOONGHYUN LEE ,  SHOGO MOCHIZUKI ,  RUQIANG BAO ,  HEMANTH JAGANNATHAN

IPC: H01L29/78 ,  H01L21/336

Abstract: A method of fabricating a semiconductor device includes forming a fin on a substrate. Source/drain regions are arranged on the substrate on opposing sides of the fin. The method includes depositing a semiconductor layer on the source/drain regions. The method includes depositing a germanium containing layer on the fin and the semiconductor layer. The method further includes applying an anneal operation configured to chemically react the semiconductor layer with the germanium containing layer and form a silicon oxide layer.

公开(公告)号：GB2579533A

公开(公告)日：2020-06-24

申请号：GB202005675

申请日：2018-10-16

Applicant: IBM

Inventor： KANGGUO CHENG ,  JUNTAO LI ,  CHOONGHYUN LEE ,  PENG XU

IPC: H01L21/336 ,  H01L21/8238 ,  H01L27/092

Abstract: Semiconductor devices and methods for making the same include patterning a stack of layers that includes channel layers, first sacrificial layers between the channel layers, and second sacrificial layers between the channel layers and the first sacrificial layers, to form one or more device regions. The first sacrificial layers are formed from a material that has a same lattice constant as a material of the first sacrificial layers and the second sacrificial layers are formed from a material that has a lattice mismatch with the material of the first sacrificial layers. Source and drain regions are formed from sidewalls of the channel layers in the one or more device regions. The first and second sacrificial layers are etched away to leave the channel layers suspended from the source and drain regions. A gate stack is deposited on the channel layers.

公开(公告)号：GB2577190A

公开(公告)日：2020-03-18

申请号：GB201916582

申请日：2018-05-11

Applicant: IBM

Inventor： CHOONGHYUN LEE ,  TAKASHI ANDO ,  VIJAY NARAYANAN ,  HEMANTH JAGANNATHAN

IPC: H01L21/02 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/10 ,  H01L29/66

Abstract: Embodiments are directed to a method and resulting structures for a dual channel complementary metal- oxide-semiconductor (CMOS) having common gate stacks. A first semiconductor fin is formed on a substrate. A second semiconductor fin is formed adjacent to the first semiconductor fin on the substrate. An oxide layer is formed over the first and second semiconductor fins and annealed at a temperature effective to increase a germanium concentration of the second semiconductor fin. The annealing process is selective to the second semiconductor fin and does not increase a germanium concentration of the first semiconductor fin.

公开(公告)号：GB2603608A

公开(公告)日：2022-08-10

申请号：GB202117331

申请日：2021-12-01

Applicant: IBM

Inventor： JINGYUN ZHANG ,  TAKASHI ANDO ,  CHOONGHYUN LEE ,  ALEXANDER REZNICEK

IPC: H01L29/06 ,  H01L21/02 ,  H01L21/28 ,  H01L21/3115 ,  H01L21/8238 ,  H01L29/423

Abstract: A method including forming nanosheet stacks 20 on a substrate 10, each nanosheet stack 20 including alternating layers of sacrificial semiconductor material and semiconductor channel material 18, removing sacrificial semiconductor material layers of the nanosheet stacks 20, forming a gate dielectric 24 surrounding the semiconductor channel layers 18 of the nanosheet stacks 20, and crystalizing the gate dielectric of a subset of the nanosheet stacks 20. The crystalized gate dielectric 32 may be formed by an annealing process. A dipole layer 34 may be formed over the gate dielectric 24 such that it surrounds the semiconductor channel layers 18, and the dipole material 34 may be diffused into the non-crystalized gate dielectric 24 of a second subset of stacks by a process of annealing. The different processes applied to the subsets of stacks may fabricate nanosheet transistors with different threshold voltages. The sacrificial semiconductor material may be silicon germanium, and the nanosheet stacks may form a FET or CMOS.

公开(公告)号：GB2594428A

公开(公告)日：2021-10-27

申请号：GB202112164

申请日：2020-01-28

Applicant: IBM

Inventor： CHOONGHYUN LEE ,  TAKASHI ANDO ,  ALEXANDER REZNICEK ,  JINGYUN ZHANG ,  POUYA HASHEMI

IPC: H01L45/00 ,  G11C13/00 ,  H01L27/24 ,  H01L29/66 ,  H01L29/78

Abstract: A resistive memory structure is provided. The resistive memory structure includes a vertical fin on a substrate, wherein the sidewalls of the vertical fin each have a {100} crystal face. The resistive memory structure further includes a fin template on the vertical fin, and a gate structure on the vertical fin. The resistive memory structure further includes a top source/drain on opposite sidewalls of the vertical fin, and a bottom electrode layer on the top source/drain, wherein the bottom electrode layer is on opposite sides of the fin template. The resistive memory structure further includes a first middle resistive layer on a portion of the bottom electrode layer, a top electrode layer on the first middle resistive layer, and a first electrical contact on a portion of the bottom electrode layer.

公开(公告)号：GB2575598B

公开(公告)日：2021-10-06

申请号：GB201915742

申请日：2018-04-19

Applicant: IBM

Inventor： SHOGO MOCHIZUKI ,  CHOONGHYUN LEE ,  RUQIANG BAO ,  HEMANTH JAGANNATHAN

IPC: H01L29/78

Abstract: Embodiments are directed to a method and resulting structures for a vertical field effect transistor (VFET) having a reduced bottom contact resistance. A multilayered bottom doped region having alternating doped layers and doped sacrificial layers is formed on a substrate. One or more cavities are formed by removing portions of the doped sacrificial layers. A bottom contact is formed over the multilayered bottom doped region. The bottom contact includes one or more conductive flanges that fill the cavities.

公开(公告)号：GB2578061A

公开(公告)日：2020-04-15

申请号：GB202000159

申请日：2018-06-07

Applicant: IBM

Inventor： RUQIANG BAO ,  CHOONGHYUN LEE ,  SHOGO MOCHIZUKI ,  CHUN WING YEUNG

IPC: H01L27/04

Abstract: A method of forming multiple vertical transport fin field effect transistors (VT FinFETs) having different channel lengths, including, forming a vertical fin on a first region of a substrate and a vertical fin on a second region of the substrate, forming a cover block on the vertical fin on the second region of the substrate, forming a first bottom source/drain on the first region of the substrate, wherein the first bottom source/drain covers a lower portion of the vertical fin on the first region, removing the cover block, and forming a second bottom source/drain in the second region of the substrate, wherein the second bottom source/drain is below the surface of the substrate, wherein the second bottom source/drain does not cover a lower portion of the vertical fin on the second region.

公开(公告)号：GB2578061B

公开(公告)日：2021-12-01

申请号：GB202000159

申请日：2018-06-07

Applicant: IBM

Inventor： RUQIANG BAO ,  CHOONGHYUN LEE ,  SHOGO MOCHIZUKI ,  CHUN WING YEUNG

IPC: H01L27/04 ,  H01L21/8234 ,  H01L27/088

Abstract: A method of forming multiple vertical transport fin field effect transistors (VT FinFETs) having different channel lengths, including, forming a vertical fin on a first region of a substrate and a vertical fin on a second region of the substrate, forming a cover block on the vertical fin on the second region of the substrate, forming a first bottom source/drain on the first region of the substrate, wherein the first bottom source/drain covers a lower portion of the vertical fin on the first region, removing the cover block, and forming a second bottom source/drain in the second region of the substrate, wherein the second bottom source/drain is below the surface of the substrate, wherein the second bottom source/drain does not cover a lower portion of the vertical fin on the second region.