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    Nanosheet transistors with different gate dielectrics and workfunction metals
    1.
    发明专利
    Nanosheet transistors with different gate dielectrics and workfunction metals 未知

    公开(公告)号：GB2579533B

    公开(公告)日：2020-11-04

    申请号：GB202005675

    申请日：2018-10-16

    Applicant: IBM

    Inventor： KANGGUO CHENG ,  JUNTAO LI ,  CHOONGHYUN LEE ,  PENG XU

    IPC: H01L21/336 ,  H01L21/8238 ,  H01L27/092

    Abstract: Integrated chips include vertically stacked channel layers, with a first stack in a first device region and a second stack in a second device region. A first dielectric layer is formed conformally on the vertically stacked channel layers in the first device region. A second dielectric layer is formed conformally on the vertically stacked channel layers in the second device region. Gate conductors are formed around the vertically stacked channel layers in both the first device region and the second device region, filling a space between surfaces of the respective first dielectric layer and second dielectric layer.

    Bottom-up metal gate formation on replacement metal gate finfet devices
    2.
    发明专利
    Bottom-up metal gate formation on replacement metal gate finfet devices 未知

    公开(公告)号：GB2549621B

    公开(公告)日：2018-06-13

    申请号：GB201706263

    申请日：2016-01-04

    Applicant: IBM

    Inventor： HONG HE ,  JUNLI WANG ,  CHIH-CHAO YANG ,  JUNTAO LI

    IPC: H01L21/8234 ,  H01L21/28

    Abstract: A method of fabricating a replacement metal gate in a transistor device, a fin field effect transistor (finFET), and method of fabricating a finFET device with the replacement metal gate are described. The method of fabricating the replacement metal gate includes forming a dummy gate structure over a substrate, the dummy gate structure being surrounded by an insulating layer, and removing the dummy gate structure so as to expose a trench within the insulating layer. The method also includes conformally depositing a dielectric material layer and a work function metal layer over a the insulating layer and in the trench and removing the dielectric material layer and the work function metal layer from a tip surface of the insulating layer, recessing the work function metal layer below a top of the trench, and selectively forming a gate metal only on exposed surfaces of the work function metal layer

    Phase change memory cell sidewall heater
    3.
    发明专利
    Phase change memory cell sidewall heater 未知

    公开(公告)号：GB2635490A

    公开(公告)日：2025-05-14

    申请号：GB202504146

    申请日：2023-05-18

    Applicant: IBM

    Inventor： JUNTAO LI ,  KANGGUO CHENG ,  CARL RADENS ,  CHING-TZU CHEN

    IPC: H10N70/20 ,  H10B63/10

    Abstract: A phase change memory structure with improved sidewall heater and formation thereof may be presented. Phase change materials are capable of being switched between a first structural state in which the material is in a generally amorphous solid phase, and a second structural state in which the material is in a generally crystalline solid phase in the active region of the cell. Presented herein may be a side wall heater, where the upper section extends through bilayer dielectric to contact a phase change material layer and the lower section of the sidewall heater has conductive layers in contact with the bottom electrode. The width of the sidewall heater may reflect an inverted T shape reducing the current requirement to reset the phase change material.

    Bottom-up metal gate formation on replacement metal gate finfet devices
    4.
    发明专利
    Bottom-up metal gate formation on replacement metal gate finfet devices 未知

    公开(公告)号：GB2549621A

    公开(公告)日：2017-10-25

    申请号：GB201706263

    申请日：2016-01-04

    Applicant: IBM

    Inventor： HONG HE ,  JUNLI WANG ,  CHIH-CHAO YANG ,  JUNTAO LI

    IPC: H01L21/8234 ,  H01L21/28

    Abstract: A method of fabricating a replacement metal gate in a transistor device, a fin field effect transistor (finFET), and a method of fabricating a finFET device with the replacement metal gate are described. The method of fabricating the replacement metal gate includes forming a dummy gate structure (140) over a substrate (110), the dummy gate structure (140) being surrounded by an insulating layer (120), and removing the dummy gate structure (140) so as to expose a trench (121) within the insulating layer (120). The method also includes conformally depositing a dielectric material layer (160) and a work function metal layer (170) over the insulating layer (120) and in the trench (121) and removing the dielectric material layer (160) and the work function metal layer (170) from a tip surface of the insulating layer (120), recessing the work function metal layer (170) below a top of the trench (121), and selectively forming a gate metal (190) only on exposed surfaces of the work function metal layer (170).

    Fabrication of logic devices and power devices on the same substrate
    6.
    发明专利
    Fabrication of logic devices and power devices on the same substrate 未知

    公开(公告)号：GB2582087A

    公开(公告)日：2020-09-09

    申请号：GB202007421

    申请日：2018-12-03

    Applicant: IBM

    Inventor： JUNTAO LI ,  KANGGUO CHENG ,  LIYING JLANG ,  JOHN GERARD GAUDIELLO

    IPC: H01L21/84

    Abstract: A method of forming a logic device and a power device on a substrate is provided. The method includes forming a first vertical fin on a first region of the substrate and a second vertical fin on a second region of the substrate, wherein an isolation region separates the first region from the second region, forming a dielectric under-layer segment on the second vertical fin on the second region, and forming a first gate structure on the dielectric under- layer segment and second vertical fin on the second region.

    Nanosheet transistors with different gate dielectrics and workfunction metals
    7.
    发明专利
    Nanosheet transistors with different gate dielectrics and workfunction metals 未知

    公开(公告)号：GB2579533A

    公开(公告)日：2020-06-24

    申请号：GB202005675

    申请日：2018-10-16

    Applicant: IBM

    Inventor： KANGGUO CHENG ,  JUNTAO LI ,  CHOONGHYUN LEE ,  PENG XU

    IPC: H01L21/336 ,  H01L21/8238 ,  H01L27/092

    Abstract: Semiconductor devices and methods for making the same include patterning a stack of layers that includes channel layers, first sacrificial layers between the channel layers, and second sacrificial layers between the channel layers and the first sacrificial layers, to form one or more device regions. The first sacrificial layers are formed from a material that has a same lattice constant as a material of the first sacrificial layers and the second sacrificial layers are formed from a material that has a lattice mismatch with the material of the first sacrificial layers. Source and drain regions are formed from sidewalls of the channel layers in the one or more device regions. The first and second sacrificial layers are etched away to leave the channel layers suspended from the source and drain regions. A gate stack is deposited on the channel layers.

    TRANSISTOR DE NANOFOLHAS COM PILHA DE PORTA ASSIMÉTRICA
    8.
    发明专利
    TRANSISTOR DE NANOFOLHAS COM PILHA DE PORTA ASSIMÉTRICA 未知

    公开(公告)号：BR112022021777A2

    公开(公告)日：2022-12-13

    申请号：BR112022021777

    申请日：2021-04-30

    Applicant: IBM

    Inventor： RUILONG XIE ,  CARL RADENS ,  KANGGUO CHENG ,  JUNTAO LI ,  DECHAO GUO ,  TAO LI ,  TSUNG-SHENG KANG

    IPC: H01L29/78 ,  H01L21/336

    Abstract: TRANSISTOR DE NANOFOLHAS COM PILHA DE PORTA ASSIMÉTRICA. Métodos e estruturas resultantes para dispositivos de nanofolhas com pilhas de portas assimétricas são descritos. Uma pilha de nanofolhas (102) é formada sobre um substrato (104). A pilha de nanofolhas (102) inclui camadas semicondutoras alternadas (108) e camadas de sacrifício (110). Um revestimento de sacrifício (202) é formado sobre a pilha de nanofolhas (102) e uma estrutura de porta dielétrica (204) é formada sobre a pilha de nanofolhas (102) e o revestimento de sacrifício (202). Um primeiro espaçador interno (302) é formado em uma parede lateral das camadas de sacrifício (110). Uma porta (112) é formada sobre regiões de canal da pilha de nanofolhas (102). A porta (112) inclui uma ponte condutora que se estende sobre o substrato (104) em uma direção ortogonal à pilha de nanofolhas (102). Um segundo espaçador interno (902) é formado em uma parede lateral do portão (112). O primeiro espaçador interno (302) é formado antes da pilha de portas (112), enquanto o segundo espaçador interno (902) é formado depois e, consequentemente, a pilha de portas (112) é assimétrica.

    Fabrication of logic devices and power devices on the same substrate
    9.
    发明专利
    Fabrication of logic devices and power devices on the same substrate 未知

    公开(公告)号：GB2582087B

    公开(公告)日：2022-03-30

    申请号：GB202007421

    申请日：2018-12-03

    Applicant: IBM

    Inventor： JUNTAO LI ,  KANGGUO CHENG ,  LIYING JLANG ,  JOHN GERARD GAUDIELLO

    IPC: H01L21/84

    Abstract: A method of forming a logic device and a power device on a substrate is provided. The method includes forming a first vertical fin on a first region of the substrate and a second vertical fin on a second region of the substrate, wherein an isolation region separates the first region from the second region, forming a dielectric under-layer segment on the second vertical fin on the second region, and forming a first gate structure on the dielectric under-layer segment and second vertical fin on the second region.

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