中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

5 records (took 0.015 seconds)

    Storage having a plurality of simultaneously accessible locations
    1.
    发明授权
    Storage having a plurality of simultaneously accessible locations 失效
    具有同时存在的多个位置的存储

    公开(公告)号：US3643236A

    公开(公告)日：1972-02-15

    申请号：US3643236D

    申请日：1969-12-19

    Applicant: IBM

    Inventor： KOLANKOWSKY EUGENE ,  MCMAHON ROBERT F ,  PERLMAN DAVID J

    IPC: G11C8/16 ,  G11C15/00

    CPC classification number: G11C8/16

    Abstract: In a storage array wherein several locations are simultaneously accessed, each location includes a circuit settable to one of two conditions by signals on lines defining its position. Defining the storage position by three lines, ''''horizontal,'''' ''''vertical'''' and ''''diagonal,'''' each circuit may be selected by activating its diagonal line and either the horizontal or vertical line for that circuit. The storage cell is a solid-stage flip-flop with two cross-coupled active devices and additional active device for each of the three driving lines. Connections to each circuit through selected ones of the vertical and horizontal lines communicate information on the inactivated line.

    Abstract translation: 在其中几个位置被同时访问的存储阵列中，每个位置包括通过定义其位置的线上的信号可设置为两个状态之一的电路。 可以通过激活其对角线以及该电路的水平线或垂直线来将每个电路定义为“水平”，“垂直”和“对角线”三行的存储位置。 存储单元是具有两个交叉耦合有源器件的固体触发器和用于三个驱动线中的每一个的附加有源器件。 通过所选择的垂直和水平线路连接到每个电路，在灭活的线路上传送信息。

    POLYIMIDE-INSULATED CUBE PACKAGE OF STACKED SEMICONDUCTOR DEVICE CHIPS
    3.
    发明专利
    POLYIMIDE-INSULATED CUBE PACKAGE OF STACKED SEMICONDUCTOR DEVICE CHIPS 未知

    公开(公告)号：CA2118994A1

    公开(公告)日：1994-12-22

    申请号：CA2118994

    申请日：1994-03-14

    Applicant: IBM

    Inventor： BERTIN CLAUDE L ,  FARRAR PAUL A SR ,  HOWELL WAYNE J ,  MILLER CHRISTOPHER P ,  PERLMAN DAVID J

    IPC: H01L25/00 ,  H01L21/98 ,  H01L23/52 ,  H01L25/065 ,  H01L27/02 ,  H01L23/50 ,  H01L21/82

    Abstract: POLYIMIDE-INSULATED CUBE PACKAGE OF STACKED SEMICONDUCTOR DEVICE CHIPS A cube package of stacked silicon semiconductor chips. To accommodate cube packaging, a metal transfer layer is added over the passivated chip face to bring all of the surface electrical contacts to a common chip edge. The metal transfer layer is insulated from the chip face and from the adjacent chip in the stack by polymer layers having a low dielectric constant, and a thermal expansion coefficient matching that of the stacked chips. An adhesive polymer layer is added to strengthen the bond between the first polymer layers and the adjacent chip in the stack, by deposition of the adhesive layer and partial cure at the wafer level, and then full cure when the chips are stacked together to form the cube.

    4.
    发明专利
    未知

    公开(公告)号：FR2071924A1

    公开(公告)日：1971-09-24

    申请号：FR7036830

    申请日：1970-10-06

    Applicant: IBM

    Inventor： KOLANKOWSKY EUGENE ,  MC MAHON ROBERT F ,  PERLMAN DAVID J

    IPC: G11C8/16 ,  G11C7/00

    Abstract: In a storage array wherein several locations are simultaneously accessed, each location includes a circuit settable to one of two conditions by signals on lines defining its position. Defining the storage position by three lines, "horizontal," "vertical" and "diagonal," each circuit may be selected by activating its diagonal line and either the horizontal or vertical line for that circuit. The storage cell is a solid-stage flip-flop with two cross-coupled active devices and additional active device for each of the three driving lines. Connections to each circuit through selected ones of the vertical and horizontal lines communicate information on the inactivated line.

Patent Agency Ranking