公开(公告)号：MY123248A

公开(公告)日：2006-05-31

申请号：MYPI9904527

申请日：1999-10-20

Applicant: IBM

Inventor： BARTH JOHN E JR ,  BERTIN CLAUDE L ,  DREIBELBIS JEFFREY H ,  ELLIS WAYNE F ,  HOWELL WAYNE J ,  HEDBERG ERIK L ,  KALTER HOWARD LEO ,  TONTI WILLIAM R ,  WHEATER DONALD L

IPC: G11C29/00 ,  H01L21/66 ,  G01R31/28 ,  G01R31/319

Abstract: WAFER TEST AND BURN-IN IS ACCOMPLISHED WITH STATE MACHINE OR PROGRAMMABLE TEST ENGINES (29) LOCATED ON THE WAFER (26) BEING TESTED. EACH TEST ENGINE REQUIRE LESS THAN 10 CONNECTIONS AND EACH TEST ENGINE CAN BE CONNECTED TO A PLURALITY OF CHIPS (28-28", 28A-28E), SUCH AS A ROW OR A COLUMN OF CHIPS ON THE WAFER. THUS, THE NUMBER OF PADS (1-8) OF THE WAFER THAT MUST BE CONNECTED FOR TEST IS SUBSTANTIALLY REDUCED WHILE A LARGE DEGREE OF PARALLEL TESTING IS STILL PROVIDED. THE TEST ENGINES ALSO PERMIT ON-WAFER ALLOCATION OF REDUNDANCY IN PARALLEL SO THAT FAILING CHIPS CAN BE REPAIRED AFTER BURN-IN COMPLETE. IN ADDITION, THE PROGRAMMABLE TEST ENGINES CAN HAVE THEIR CODE ALTERED SO TEST PROGRAMS CAN BE MODIFIED TO ACCOUNT FOR NEW INFORMATION AFTER THE WAFER HAS BEEN FABRICATED. THE TEST ENGINES ARE USED DURING BURN-IN TO PROVIDE HIGH FREQUENCY WRITE SIGNALS TO DRAM ARRAYS THAT PROVIDE A HIGHER EFFECTIVE VOLTAGE TO THE ARRAYS, LOWERING THE TIME REQUIRED FOR BURN-IN. CONNECTIONS TO THE WAFER AND BETWEEN TEST ENGINES AND CHIPS ARE PROVIDED ALONG A MEMBERANE (20-20') ATTACHED TO THE WAFER. MEMBRANE CONNECTORS (31-31") CAN BE FORMED OR OPENED AFTER THE MEMBRANE IS CONNECTED TO THE WAFER SO SHORTED CHIPS CAN BE DISCONNECTED.PREFERABLY THE MEMBRANE REMAINS ON THE WAFER AFTER TEST, BURN-IN AND DICING TO PROVIDE A CHIP SCALE PACKAGE. THUS, THE VERY HIGH COST OF TCE MATCHED MATERIALS, SUCH AS GALSS CERAMIC CONTATCTORS, FOR WAFER BURN-IN IS AVOIDED WHILE PROVIDING BENEFIT BEYOND TEST AND BURN-IN FOR PACKAGING. (FIG. 2)

公开(公告)号：CA2118994A1

公开(公告)日：1994-12-22

申请号：CA2118994

申请日：1994-03-14

Applicant: IBM

Inventor： BERTIN CLAUDE L ,  FARRAR PAUL A SR ,  HOWELL WAYNE J ,  MILLER CHRISTOPHER P ,  PERLMAN DAVID J

IPC: H01L25/00 ,  H01L21/98 ,  H01L23/52 ,  H01L25/065 ,  H01L27/02 ,  H01L23/50 ,  H01L21/82

Abstract: POLYIMIDE-INSULATED CUBE PACKAGE OF STACKED SEMICONDUCTOR DEVICE CHIPS A cube package of stacked silicon semiconductor chips. To accommodate cube packaging, a metal transfer layer is added over the passivated chip face to bring all of the surface electrical contacts to a common chip edge. The metal transfer layer is insulated from the chip face and from the adjacent chip in the stack by polymer layers having a low dielectric constant, and a thermal expansion coefficient matching that of the stacked chips. An adhesive polymer layer is added to strengthen the bond between the first polymer layers and the adjacent chip in the stack, by deposition of the adhesive layer and partial cure at the wafer level, and then full cure when the chips are stacked together to form the cube.