公开(公告)号：DE69836307T2

公开(公告)日：2007-04-26

申请号：DE69836307

申请日：1998-09-15

Applicant: IBM

Inventor： ANDREWS LAWRENCE P ,  BECKMAN RICHARD CLYDE ,  ENG ROBERT CHIH-TSIN ,  LINGER JUDITH MARIE ,  PETTY JOSEPH C ,  SINIBALDI JOHN CLAUDE ,  TURBEVILLE GARY L ,  WILLIAMS KEVIN BRADLEY

IPC: G06F13/24 ,  G06F15/16 ,  G06F13/00 ,  G06F15/177 ,  H04L12/66

Abstract: A pair of communications adapters each include a number of digital signal processors (12) and network interface circuits (24) for the attachment of a multi-channel telephone line. A bus connecting the communications adapters can carry data between a network line attached to one of the adapters and the digital signal processors of the other adapter. The digital signal processors on each card are connected to a host, or controller, processor (2). Each digital signal processor interrupts its host processor by transmitting an interrupt control block as data to a data memory of the host processor, and by subsequently sending an interrupt causing the host processor to examine the data memory. Preferably, the interrupt control block includes data representing a number of requested interrupts.

公开(公告)号：DE69836307D1

公开(公告)日：2006-12-14

申请号：DE69836307

申请日：1998-09-15

Applicant: IBM

Inventor： ANDREWS LAWRENCE P ,  BECKMAN RICHARD CLYDE ,  ENG ROBERT CHIH-TSIN ,  LINGER JUDITH MARIE ,  PETTY JOSEPH C ,  SINIBALDI JOHN CLAUDE ,  TURBEVILLE GARY L ,  WILLIAMS KEVIN BRADLEY

IPC: G06F13/24 ,  G06F15/16 ,  G06F13/00 ,  G06F15/177 ,  H04L12/66

Abstract: A pair of communications adapters each include a number of digital signal processors (12) and network interface circuits (24) for the attachment of a multi-channel telephone line. A bus connecting the communications adapters can carry data between a network line attached to one of the adapters and the digital signal processors of the other adapter. The digital signal processors on each card are connected to a host, or controller, processor (2). Each digital signal processor interrupts its host processor by transmitting an interrupt control block as data to a data memory of the host processor, and by subsequently sending an interrupt causing the host processor to examine the data memory. Preferably, the interrupt control block includes data representing a number of requested interrupts.