公开(公告)号：DE3484634D1

公开(公告)日：1991-07-04

申请号：DE3484634

申请日：1984-06-15

Applicant: IBM

Inventor： GOODING DAVID NORMAN ,  JACKOWSKI STEFAN PETER ,  MOYER JAMES THEODORE ,  PLANT III JAMES WALTER

IPC: H04L1/00 ,  G06F11/10

Abstract: A failure detection apparatus is disclosed for detecting the existence of abnormal circuit conditions in a circuit, the abnormal condition causing erroneous data to be transmitted from one circuit to another circuit, via interface lines. Since spare interface lines are not available, the existing interface lines (11) must be used to determine the accuracy of the transmitted data. A gate line (13), interconnecting adjacent intergrated circuits (10, 12), gates the odd and the even data bytes of the data from the one adjacent integrated circuit to another. If the gate line fails, or otherwise experiences an abnormal circuit condition, the odd and the even data bytes will not be gated from the one adjacent integrated circuit to the other in the proper sequence. With the present invention, the proper sequence is checked. The even data bytes are transmitted along the existing interface lines from the one adjacent integrated circuit to the other with an odd parity; however, the odd data bytes are transmitted along the existing interface lines with an even parity. The receiving integrated circuit determines whether the even data bytes were received with the odd parity and whether the odd data bytes were received with the even parity. An error signal is generated when the even and odd data bytes are not received with the odd and even parity, respectively. The error signal indicates the existence of the failure gate line.