公开(公告)号：DE2457553A1

公开(公告)日：1975-07-10

申请号：DE2457553

申请日：1974-12-05

Applicant: IBM

Inventor： GOODING DAVID NORMAN

IPC: G06F9/30 ,  G06F1/10 ,  G06F1/12 ,  G06F1/04

Abstract: Clocking apparatus for complex and extensive data processing systems in which the functional logic circuit units are each provided with individual clocking circuits and the several clocking circuits are activated by a central control unit. Operation of the individual clock circuits is initiated by control unit signals and each clock circuit operates at an independent rate. The clocking system is readily adaptable to computer systems using large scale integration (LSI) since the clock circuits can be made a portion of each LSI chip and operated to control the functional logic circuits on that chip. At the conclusion of a functional cycle, a completion signal is transmitted to the central control unit which can then generate additional clock initiation signals as required. The clock circuits also include additional delay circuits which can be activated to add predetermined amounts of delay between selected clock output signals to permit remotely adapting the clock timing control to the requirements of a functional logic unit.

公开(公告)号：DE3484634D1

公开(公告)日：1991-07-04

申请号：DE3484634

申请日：1984-06-15

Applicant: IBM

Inventor： GOODING DAVID NORMAN ,  JACKOWSKI STEFAN PETER ,  MOYER JAMES THEODORE ,  PLANT III JAMES WALTER

IPC: H04L1/00 ,  G06F11/10

Abstract: A failure detection apparatus is disclosed for detecting the existence of abnormal circuit conditions in a circuit, the abnormal condition causing erroneous data to be transmitted from one circuit to another circuit, via interface lines. Since spare interface lines are not available, the existing interface lines (11) must be used to determine the accuracy of the transmitted data. A gate line (13), interconnecting adjacent intergrated circuits (10, 12), gates the odd and the even data bytes of the data from the one adjacent integrated circuit to another. If the gate line fails, or otherwise experiences an abnormal circuit condition, the odd and the even data bytes will not be gated from the one adjacent integrated circuit to the other in the proper sequence. With the present invention, the proper sequence is checked. The even data bytes are transmitted along the existing interface lines from the one adjacent integrated circuit to the other with an odd parity; however, the odd data bytes are transmitted along the existing interface lines with an even parity. The receiving integrated circuit determines whether the even data bytes were received with the odd parity and whether the odd data bytes were received with the even parity. An error signal is generated when the even and odd data bytes are not received with the odd and even parity, respectively. The error signal indicates the existence of the failure gate line.

公开(公告)号：DE2626432A1

公开(公告)日：1977-01-13

申请号：DE2626432

申请日：1976-06-12

Applicant: IBM

Inventor： GOODING DAVID NORMAN ,  SHIMP EVERETT MONTAGUE

IPC: G06F7/48 ,  G06F7/493 ,  G06F7/494 ,  G06F7/50 ,  G06F7/508 ,  G06F5/00

Abstract: 1512476 Arithmetic units INTERNATIONAL BUSINESS MACHINES CORP 6 May 1976 [17 June 1975] 18555/76 Heading G4A An arithmetic unit capable of operating on operands in zoned or packed BCD format as well as binary comprises an adder 20 having input modifying circuitry 23, 33 which so modifies the zone and/or sign fields of the zoned or packed BCD operands that carries can be propagated through those fields, and an output corrector 50 which restores the original zone and/or sign field coding. The sign fields of the two input operands A, B are examined in a sign handler together with the requested add/subtract operation command to control complementing-circuits in the B operand modifier 33 according to whether or not two operands of the same or different signs are to be added or subtracted. In the zoned (EBDIC) format, 4-bit digit fields alternate with 4-bit zone fields coded 1111, the zone field in the lowest order byte being a sign field which is coded 1111 (hex F) for positive and 1101 (hex D) for negative. For operation in zoned format the A operand modifier forces the zone and sign fields to 0000 whereas the B operand modifier forces the sign field to 1111 and leaves the zone fields unchanged at the same code. The digit codes are unchanged for the A operand and are either complemented (for subtraction) or augmented by six (for decimal addition) for the B operand. In the packed BCD format the lowest order 4-bit field is coded 1100 (hex C) for positive and 1101 (hex D) for negative, and the A and B operand modifiers force the sign fields to 0000 and 1111 (hex F) respectively. The adder 20 is a conventional carry look-ahead parallel binary adder (or subtractor), e.g. 4 bytes wide and provides inter-field carries C0-C7. Any odd numbered carry produced from the combination of a pair of zoned digit fields can propagate through the intervening zone field to the next digit field, and a carry in CIN can propagate through the packed BCD sign field to the lowest order digit field. The output corrector 50 has control inputs 26-28, 46 which cause it to force all zone fields to 1111 and/or the sign field to the appropriate code (normally the same as the A operand) as appropriate for zoned or packed BCD operation, and to leave unchanged each digit field or to subtract 6 (or add 10) according to the presence or absence of corresponding carries. In the case where B is numerically greater than A and subtraction is performed, the absence of CO is detected at 65 and causes a recomplementing operation to be performed in which the contents of the output register 53 are loaded into the B register, the A modifier forces all A operand bits to zero, the B modifier complements and the output corrector 50 inverts the original sign of the output. For operation with operands of greater width than the adder, two or more passes are made using different parts of the operands, the operation of modifiers 23, 33 being changed for the second and any subsequent passes to allow for the fact that the sign fields are only present in the first pass. The status of CO is stored in a latch 70 after each pass to form the input CIN for the next pass if any.

公开(公告)号：BR8402763A

公开(公告)日：1985-05-14

申请号：BR8402763

申请日：1984-06-07

Applicant: IBM

Inventor： GOODING DAVID NORMAN ,  JACKWSKI STEFAN PETER ,  MOOER JAMES THEODORE ,  PLAT JAMES WALTER III

IPC: H04L1/00 ,  G06F11/10

Abstract: A failure detection apparatus is disclosed for detecting the existence of abnormal circuit conditions in a circuit, the abnormal condition causing erroneous data to be transmitted from one circuit to another circuit, via interface lines. Since spare interface lines are not available, the existing interface lines (11) must be used to determine the accuracy of the transmitted data. A gate line (13), interconnecting adjacent intergrated circuits (10, 12), gates the odd and the even data bytes of the data from the one adjacent integrated circuit to another. If the gate line fails, or otherwise experiences an abnormal circuit condition, the odd and the even data bytes will not be gated from the one adjacent integrated circuit to the other in the proper sequence. With the present invention, the proper sequence is checked. The even data bytes are transmitted along the existing interface lines from the one adjacent integrated circuit to the other with an odd parity; however, the odd data bytes are transmitted along the existing interface lines with an even parity. The receiving integrated circuit determines whether the even data bytes were received with the odd parity and whether the odd data bytes were received with the even parity. An error signal is generated when the even and odd data bytes are not received with the odd and even parity, respectively. The error signal indicates the existence of the failure gate line.

公开(公告)号：DE2625113A1

公开(公告)日：1976-12-30

申请号：DE2625113

申请日：1976-06-04

Applicant: IBM

Inventor： GOODING DAVID NORMAN ,  SHIMP EVERETT MONTAGUE

IPC: G06F7/00 ,  G06F11/30 ,  G06F12/14 ,  G06F11/00

Abstract: Data processing circuitry for performing two serially related arithmetic operations during one and the same machine control cycle and employing an independent zone parallel type arithmetic unit capable of simultaneously performing independent arithmetic operations in the different zones thereof. Data transfer circuitry is provided for immediately supplying the output result of a first arithmetic unit zone back to the input of a second arithmetic unit zone for immediately producing a second and different result. Such transfer circuitry is constructed to operate in an asynchronous manner so that the first result is supplied back to the input of the second arithmetic unit zone as soon as it becomes available at the output of the first arithmetic zone. Thus, a second result, which is dependent on the first result, is produced during the same machine control cycle as the first result. This data processing circuitry is particularly useful for providing storage protection for a data processor. In such case, the current storage address and a requested storage access length value are supplied to the first arithmetic unit zone for producing a new address representing the upper extent of the storage access request. The resultant new address is immediately supplied back to the input of the second arithmetic unit zone for combining same with an upper limit address for immediately producing an upper bounds extent error when the new address exceeds the upper limit address.

公开(公告)号：DE2616717A1

公开(公告)日：1976-11-11

申请号：DE2616717

申请日：1976-04-15

Applicant: IBM

Inventor： GOODING DAVID NORMAN ,  SHIMP EVERETT MONTAGUE

IPC: G06F7/505 ,  G06F7/50 ,  G06F7/508

Abstract: A carry look-ahead parallel digital adder having a relatively wide overall data flow width and a pair of automatically adjustable boundary mechanisms for subdividing the adder into plural independent operating zones of variable width and variable location. Anywhere from one to three independent zones may be obtained. Independent external carry-in and carry-out lines are provided for each zone and the connecting points for such lines are automatically shifted in step with the movement of the zone boundaries.