公开(公告)号：JP2004087100A

公开(公告)日：2004-03-18

申请号：JP2003275677

申请日：2003-07-16

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： LOUIS RUUCHEN SHEW ,  FREDEMAN GREGORY ,  HWANG CHORNG-LII ,  KIRIHATA TOSHIAKI K ,  PONTIUS DALE E

IPC: G11C11/413 ,  G11C11/401 ,  G11C29/00 ,  G11C29/04

CPC classification number: G11C29/846 ,  G11C2207/104

Abstract: PROBLEM TO BE SOLVED: To provide an effective column restoration system which replaces a defective column element with a redundant element.
SOLUTION: A column redundant device 10 includes a fuse information storage device for every individual microcell to store fuse information indicating the location of any one of defective elements. A first bank address decoding mechanism decodes a reading bank address corresponding to a first microcell and a second bank address decoding mechanism decodes a writing bank address corresponding to a second microcell. When at least one defective column element is included in the first microcell, the device 10 generates an internal column address corresponding to at least one defective column element in the first microcell. Similarly, the device 10 generates an internal column address corresponding to at least one defective column element in the second microcell when at least one defective column element is included in the second microcell.
COPYRIGHT: (C)2004,JPO

公开(公告)号：JP2005339752A

公开(公告)日：2005-12-08

申请号：JP2004161135

申请日：2004-05-31

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： GORMAN KEVIN W ,  PONTIUS DALE E

IPC: G11C29/04 ,  G11C29/00

Abstract: PROBLEM TO BE SOLVED: To provide a method and structure for performing a high-speed operation in space smaller than the conventional one by avoiding the need of using scan latch for the maintenance of fuse information.
SOLUTION: An SRAM array is a portion of a scan chain and is connected to upstream and downstream latches constituting the scan chain. When data is serially read in the scan chain, the number of bits read in an embedded DRAM structure is counted. After a counter 120 counts an amount that is equal to the number of stored bits of the entire downstream scan latches in the scan chain, in this method and structure, fuse information is loaded to a shift register. When the shift register is filled, shift register contents are loaded to an SRAM line. The length of the shift register and the SRAM line is equal to that of one fuse word. Until the SRAM array is filled, the processes of shift register load and SRAM array load are repeated.
COPYRIGHT: (C)2006,JPO&NCIPI

Abstract translation: 要解决的问题：提供一种用于在比常规的空间小的空间中执行高速操作的方法和结构，通过避免使用扫描锁存器来维护熔丝信息。 解决方案：SRAM阵列是扫描链的一部分，并连接到构成扫描链的上游和下游锁存器。 当在扫描链中串行读取数据时，对嵌入式DRAM结构中读取的位数进行计数。 在计数器120计数与扫描链中整个下游扫描锁存器的存储位数相等的量时，在该方法和结构中，熔丝信息被加载到移位寄存器。 当移位寄存器被填满时，移位寄存器内容被加载到SRAM行。 移位寄存器和SRAM线的长度等于一个保险丝字的长度。 在SRAM阵列被填充之前，重复移位寄存器负载和SRAM阵列负载的处理。 版权所有（C）2006，JPO＆NCIPI

公开(公告)号：CA2074879A1

公开(公告)日：1993-05-01

申请号：CA2074879

申请日：1992-07-29

Applicant: IBM

Inventor： GRUNBOK WARREN W ,  KNOWLES BILLY J ,  MILANI WILLIAM R ,  MORAN DOUGLAS R ,  PONTIUS DALE E ,  PRICE DONALD W ,  TAMLYN ROBERT ,  TING YEE-MING ,  TRAN DE ,  YEH HENRY

IPC: G06F12/06 ,  G06F13/16 ,  G11C8/12 ,  G11C8/00

Abstract: KI9-91-010 MEMORY SYSTEM AND UNIQUE MEMORY CHIP ALLOWING ISLAND INTERLACE A memory system and a unique memory chip is disclosed wherein multiple islands on a chip can be separately accessed by separate island controllers whereby concurrent use of the several islands or arrays on a chip can be achieved.

公开(公告)号：BR9203918A

公开(公告)日：1993-05-04

申请号：BR9203918

申请日：1992-10-08

Applicant: IBM

Inventor： GRUNBOK WARREN W ,  KNOWLES BILLY J ,  MILANI WILLIAM R ,  MORAN DOUGLAS R ,  PONTIUS DALE E ,  PRICE DONALD W ,  TAMLYN ROBERT ,  TING YEE-MINE ,  TRAN DE ,  YEH HENRY

IPC: G06F12/06 ,  G06F13/16 ,  G11C8/12 ,  G11C7/00

Abstract: A memory system (15) and a memory chip is disclosed wherein multiple islands (21) on a chip can be separately accessed by separate island controllers whereby concurrent use of the several islands or arrays on a chip can be achieved.