中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

52 records (took 0.035 seconds)

    Method for recording and reproducing data in probe-based data storage device, computer program and apparatus, and probe-based data storage device
    3.
    发明专利
    Method for recording and reproducing data in probe-based data storage device, computer program and apparatus, and probe-based data storage device 有权
    用于在基于数据存储设备，计算机程序和设备中记录和再现数据的方法和基于探测的数据存储设备

    公开(公告)号：JP2008135160A

    公开(公告)日：2008-06-12

    申请号：JP2007302031

    申请日：2007-11-21

    Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

    Inventor： POZIDIS CHARALAMPOS ,  EVANGELOS S ELEFTHERIOU

    IPC: G11B9/14

    CPC classification number: G11B9/14 ,  B82Y10/00 ,  G11B11/007

    Abstract: PROBLEM TO BE SOLVED: To provide methods and apparatus for recording/reproducing data in a device in which application of a write signal causes formation of an indentation on a storage surface by a probe of the probe-based data storage device.
    SOLUTION: Information is stored in the form of grooves of variable length separated by lands of variable length. By applying a series of write signals at respective probe-positions on the storage surface, a first value (generally "1") which is a series of n>1 successive bits sequence in a recording signal is recoded. These probe-positions are spaced at w

    Abstract translation: 要解决的问题：提供用于在写入信号的应用通过基于探测器的数据存储装置的探头在存储表面上形成凹陷的装置中记录/再现数据的方法和装置。

    解决方案：信息以可变长度分隔的可变长度的槽的形式存储。 通过在存储表面上的相应探针位置应用一系列写信号，记录作为记录信号中的一系列n> 1个连续位序列的第一值（通常为“1”）被重新编码。 这些探针位置间距为w <= M，其中，M为压痕合并距离，以便产生的压痕合并，形成跨越n个回读采样位置的存储表面中的凹槽。 版权所有（C）2008，JPO＆INPIT

    METHOD FOR MANUFACTORING A CARBON-BASED MEMORY ELEMENT AND MEMORY ELEMENT
    6.
    发明申请
    METHOD FOR MANUFACTORING A CARBON-BASED MEMORY ELEMENT AND MEMORY ELEMENT 审中-公开
    用于制造基于碳的存储元件和存储元件的方法

    公开(公告)号：WO2012001599A2

    公开(公告)日：2012-01-05

    申请号：PCT/IB2011052790

    申请日：2011-06-24

    Applicant: IBM ,  CAIMI DANIELE ,  ELEFTHERIOU EVANGELOS S ,  POZIDIS CHARALAMPOS ,  ROSSEL CHRISTOPHE P ,  SEBASTIAN ABU

    Inventor： CAIMI DANIELE ,  ELEFTHERIOU EVANGELOS S ,  POZIDIS CHARALAMPOS ,  ROSSEL CHRISTOPHE P ,  SEBASTIAN ABU

    IPC: H01L45/00

    CPC classification number: H01L45/16 ,  G11C13/0002 ,  G11C2213/15 ,  G11C2213/35 ,  H01L45/04 ,  H01L45/1253 ,  H01L45/149

    Abstract: A method for manufacturing a resistive memory element (1) comprises: providing a storage layer (2) comprising a resistance changeable material; said resistance changeable material comprising carbon; providing contact layers (3, 4) for contacting the storage layer (2), wherein the storage layer (2) is disposed between a bottom contact layer (3) and a top contact layer (4); and doping the resistance changeable material with a dopant material. A resistive memory element (1) includes a bottom contact layer (3), a top contact layer (4) and a storage layer (2) disposed between the bottom contact layer (3) and the top contact layer (4), wherein the storage layer (2) comprises a resistance changeable material that is doped with a dopant material.

    Abstract translation: 一种用于制造电阻式存储元件（1）的方法，包括：提供包括电阻可变材料的存储层（2）; 所述电阻变化材料包含碳; 提供用于接触所述存储层（2）的接触层（3,4），其中所述存储层（2）设置在底部接触层（3）和顶部接触层（4）之间; 并用掺杂剂材料掺杂电阻可变材料。 电阻式存储器元件（1）包括底部接触层（3），顶部接触层（4）和设置在底部接触层（3）和顶部接触层（4）之间的存储层（2），其中 存储层（2）包括掺杂有掺杂剂材料的电阻可变材料。

    Estimation of level-thresholds for memory cells
    8.
    发明专利
    Estimation of level-thresholds for memory cells 未知

    公开(公告)号：GB2518632A

    公开(公告)日：2015-04-01

    申请号：GB201317081

    申请日：2013-09-26

    Applicant: IBM

    Inventor： MITTELHOLZER THOMAS ,  PAPANDREOU NIKOLAOS ,  POZIDIS CHARALAMPOS

    IPC: G11C11/56 ,  G06F11/10 ,  G11C13/00 ,  G11C16/34

    Abstract: Methods (figure 4) and apparatus 6 for determining level thresholds for q-level memory cells, or multi level cells (MLC). A plurality of the memory cells are read to obtain respective read signal components (20, figure 4). The read signal components are processed by means of a vector generator 10 in dependence on signal level to produce a signal level vector, comprising a series of elements, indicative of the distribution of read signal components in order of signal level. Signal level binning of the read signal components may also be carried out. The signal level vector is scanned 11 with a sliding window of length greater than the spacing of successive window positions in the scan. At each window position, a metric Mi is calculated in dependence on the elements of the signal level vector in the window. A level-threshold for successive memory cell levels is then determined in a threshold identifier 12, in dependence on the variation of the metric, over the scan. At each window position a reference may be determined based on the average or mean of the elements. The metric may then be calculated from the difference between each element value and the reference value (24 figure 4). The system may comprise phase change memory cells or flash memory cells. The level thresholds are determined from the largest local maxima in the metric variation over the scan (figure 5). The memory cells may be encoded so as to store qary symbols of N-symbol codewords.

    Method and apparatus for read measurement of a plurality of resistive memory cells
    9.
    发明专利
    Method and apparatus for read measurement of a plurality of resistive memory cells 未知

    公开(公告)号：GB2510339A

    公开(公告)日：2014-08-06

    申请号：GB201301621

    申请日：2013-01-30

    Applicant: IBM

    Inventor： PAPANDREOU NIKOLAOS ,  POZIDIS CHARALAMPOS ,  SEBASTIAN ABU

    IPC: G11C13/00 ,  G11C11/56

    Abstract: A method and apparatus for read measurement or data sensing a plurality N of resistive memory cells, having a plurality K of programmable levels (figures 2-4), including applying a first read voltage to each of the N memory cells and measuring a first read current, (101 figure 1). A further step (102 figure 1) is executed to determine a respective second read voltage based on the first read current measured at the memory cell and a target read current determined for the memory cell for each of the N memory cells. A subsequent step (103 figure 1) involves applying the respective determined second read voltage to the memory cell for obtaining a second read current for each of the N memory cells. The second read voltage may be determined such that the second read current is constant for all memory cells programmed with the same level or may have one respective target current for each of the K programmed levels. The target currents may be determined as the level means of the first read currents, as blind estimations or may involve the use of a number of identical reference cells. The method may also include data mapping of read currents to the respective cells. The apparatus for measurement includes a voltage generator 13 for applying a bias to the bit line connected to the resistive memory, a current detector 14 for measuring the current through the resistive memory device 11 and a measurement controller 15 all of which may be computerised.

Patent Agency Ranking