公开(公告)号：WO2014033567A1

公开(公告)日：2014-03-06

申请号：PCT/IB2013056276

申请日：2013-07-31

Applicant: IBM ,  IBM JAPAN ,  IBM RES GMBH

Inventor： DESPONT MICHEL ,  GROGG DANIEL ,  HAGLEITNER CHRISTOPH ,  PU YU

IPC: H03K19/02

CPC classification number: H03K19/02 ,  H03K19/20

Abstract: The invention refers to a dynamic logic gate comprising a nano-electro-mechanical- switch, preferably a four-terminal-nano-electro-mechanical-switch. The invention further refers to dynamic logic cascade circuits comprising such a dynamic logic gate. In particular, embodiments of the invention concern dynamic logic cascade circuits comprising single or dual rail dynamic logic gates.

Abstract translation: 本发明涉及一种包括纳米机电开关，优选四端子纳米机电开关的动态逻辑门。 本发明还涉及包括这种动态逻辑门的动态逻辑级联电路。 特别地，本发明的实施例涉及包括单轨或双轨动态逻辑门的动态逻辑级联电路。

公开(公告)号：GB2505467A

公开(公告)日：2014-03-05

申请号：GB201215513

申请日：2012-08-31

Applicant: IBM

Inventor： DESPONT MICHEL ,  GROGG DANIEL ,  HAGLEITNER CHRISTOPH ,  PU YU

IPC: H03K19/00 ,  H01H1/00

Abstract: The invention refers to a dynamic logic gate comprising a nano-electro-mechanical switch (NEMS), preferably a four-terminal NEM switch (4T-NEMS). The NEMS comprises a cantilever beam adapted to flex in response to an actuation voltage applied between the body and the gate of the device. The invention further refers to dynamic logic cascade circuits comprising such dynamic logic gates. In particular, embodiments of the invention concern dynamic logic cascade circuits comprising single or dual rail dynamic logic gates. A NEMS allows zero leakage current when it is off so the pre-charged signal node in a dynamic logic gate can safely retain its charge, without the requirement for keeper transistors as in prior art CMOS dynamic logic circuits. The proposed NEMS adiabatic dynamic logic avoids both the leakage energy loss and the threshold voltage residue charge loss; it consumes only the adiabatic energy loss. As a result, an ultra-low energy loss close to zero is achieved.