Abstract:
PROBLEM TO BE SOLVED: To provide a tapered gate and a synthesis method for improving the quality of synthesized circuit mounting. SOLUTION: A high-performance gate library is augmented with tapered gates. The widths of the stacked devices are varied to reduce delay through some of input pins. For example in a tapered NAND gate, the bottom devices in a NFET stack are to have longer widths than the top device to achieve smaller top input to output pin delay at the expense of larger bottom input to output pin delay. The method of using synthesis algorithms modifies an input net to gate pin connections and swaps traditional non-tapered gates with tapered gates to improve the delay of timing critical paths. The latest arriving gate input net is swapped with a net connected to the top pin. The gate is then converted to a tapered gate and is given paths going through the bottom gate input(s) that are not timing critical. COPYRIGHT: (C)2003,JPO
Abstract:
PROBLEM TO BE SOLVED: To provide a method, apparatus and computer program for performing simulation of influence of a manufacturing process to electrical performance in the integrated circuit during design stage. SOLUTION: Methods, apparatus and computer program provide a fast and accurate model for simulating the effects of chemical mechanical polishing (CMP) steps during fabrication of an integrated circuit by generating a design of an integrated circuit, using a simplified model while generating the design of the integrated circuit, predicting at least one physical characteristic of the integrated circuit which results from a processing step to be used during manufacture of the integrated circuit, wherein the simplified model is derived from simulations performed prior to the design generation activities using a comprehensive simulation program used to model the physical characteristic; predicting performance of the integrated circuit using the predicted physical characteristic; and adjusting the design of the integrated circuit in dependence on the performance prediction. COPYRIGHT: (C)2010,JPO&INPIT
Abstract:
PROBLEM TO BE SOLVED: To provide a level converter for interfacing two circuits to which different power supply voltages are supplied, and an integrated circuit containing a level converter interfacing circuits in two different voltage islands. SOLUTION: Power is supplied to a first buffer 104 with a pretense power supply V, and the first buffer 104 receives an input signal 102 from a lower voltage circuit. The first buffer 104 drives a second buffer 108 to which higher power supply voltage V ddh is supplied. Power supply selecting mechanisms 120, 128 are so switched by an output 110 from the second buffer 108 that the higher power supply voltage V ddh or reduced power supply voltage V is selectively passed to the first buffer 104. COPYRIGHT: (C)2005,JPO&NCIPI
Abstract:
Methods, apparatus and computer program products provide a fast and accurate model for simulating the effects of chemical mechanical polishing (CMP) steps during fabrication of an integrated circuit by generating a design of an integrated circuit; while generating the design of the integrated circuit, using a simplified model to predict at least one physical characteristic of the integrated circuit which results from a CMP processing step to be used during manufacture of the integrated circuit, wherein the simplified model is derived from simulations performed prior to the design generation activities using a comprehensive simulation program used to model the physical characteristic; predicting performance of the integrated circuit using the predicted physical characteristic; and adjusting the design of the integrated circuit in dependence on the performance prediction.