公开(公告)号：JP2003016123A

公开(公告)日：2003-01-17

申请号：JP2002102222

申请日：2002-04-04

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーション

Inventor： CURRAN BRIAN W ,  LACEY LISA BRYANT ,  NORTHROP GREGORY A ,  PURI RUCHIR ,  STOK LEON

IPC: G06F17/50 ,  H01L21/82 ,  H03K19/096 ,  H03K19/20

CPC classification number: G06F17/505

Abstract: PROBLEM TO BE SOLVED: To provide a tapered gate and a synthesis method for improving the quality of synthesized circuit mounting.
SOLUTION: A high-performance gate library is augmented with tapered gates. The widths of the stacked devices are varied to reduce delay through some of input pins. For example in a tapered NAND gate, the bottom devices in a NFET stack are to have longer widths than the top device to achieve smaller top input to output pin delay at the expense of larger bottom input to output pin delay. The method of using synthesis algorithms modifies an input net to gate pin connections and swaps traditional non-tapered gates with tapered gates to improve the delay of timing critical paths. The latest arriving gate input net is swapped with a net connected to the top pin. The gate is then converted to a tapered gate and is given paths going through the bottom gate input(s) that are not timing critical.
COPYRIGHT: (C)2003,JPO

Abstract translation: 要解决的问题：提供一种用于提高合成电路安装质量的锥形栅极和合成方法。 解决方案：一个高性能门库增加了锥形门。 改变堆叠器件的宽度以减少一些输入引脚的延迟。 例如在锥形NAND门中，NFET堆叠中的底部器件将具有比顶部器件更长的宽度，以牺牲较大的底部输入到输出引脚延迟为代价，从而实现较小的顶部输入以输出引脚延迟。 使用合成算法的方法将输入网络修改为栅极引脚连接，并与具有锥形栅极的传统非锥形栅极交换，以改善时序关键路径的延迟。 最新的到达门输入网络与连接到顶部引脚的网络互换。 然后将栅极转换为锥形栅极，并给出通过不是时序关键的底栅输入的路径。

公开(公告)号：JP2010079896A

公开(公告)日：2010-04-08

申请号：JP2009209893

申请日：2009-09-11

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： XIANG HUA ,  ECONOMIKOS LAERTIS ,  FAYAZ MOHAMMED FAZIL ,  GRECO STEPHEN EDWARD ,  O'NEIL PATRICIA A ,  PURI RUCHIR

IPC: G06F17/50 ,  H01L21/82

CPC classification number: G06F17/5009 ,  G06F2217/12 ,  Y02P90/265

Abstract: PROBLEM TO BE SOLVED: To provide a method, apparatus and computer program for performing simulation of influence of a manufacturing process to electrical performance in the integrated circuit during design stage.
SOLUTION: Methods, apparatus and computer program provide a fast and accurate model for simulating the effects of chemical mechanical polishing (CMP) steps during fabrication of an integrated circuit by generating a design of an integrated circuit, using a simplified model while generating the design of the integrated circuit, predicting at least one physical characteristic of the integrated circuit which results from a processing step to be used during manufacture of the integrated circuit, wherein the simplified model is derived from simulations performed prior to the design generation activities using a comprehensive simulation program used to model the physical characteristic; predicting performance of the integrated circuit using the predicted physical characteristic; and adjusting the design of the integrated circuit in dependence on the performance prediction.
COPYRIGHT: (C)2010,JPO&INPIT

Abstract translation: 要解决的问题：提供一种用于在设计阶段期间对集成电路中的制造过程对电气性能的影响进行模拟的方法，装置和计算机程序。 解决方案：方法，设备和计算机程序提供了一种快速准确的模型，用于在集成电路制造过程中模拟化学机械抛光（CMP）步骤的效果，通过使用简化模型生成集成电路的设计，同时产生 集成电路的设计，预测由在集成电路的制造期间使用的处理步骤产生的集成电路的至少一个物理特性，其中简化模型是从使用 综合仿真程序用于建模物理特性; 使用预测的物理特性预测集成电路的性能; 并根据性能预测调整集成电路的设计。 版权所有（C）2010，JPO＆INPIT

公开(公告)号：JP2005160073A

公开(公告)日：2005-06-16

申请号：JP2004335488

申请日：2004-11-19

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： CORREALE ANTHONY JR ,  JOSHI RAJIV ,  KUNG DAVID S ,  PAN ZHIGANG ,  PURI RUCHIR

IPC: H03K19/0185 ,  H03K19/0948

CPC classification number: H03K19/018521 ,  H03K19/0948

Abstract: PROBLEM TO BE SOLVED: To provide a level converter for interfacing two circuits to which different power supply voltages are supplied, and an integrated circuit containing a level converter interfacing circuits in two different voltage islands.
SOLUTION: Power is supplied to a first buffer 104 with a pretense power supply V, and the first buffer 104 receives an input signal 102 from a lower voltage circuit. The first buffer 104 drives a second buffer 108 to which higher power supply voltage V
ddh is supplied. Power supply selecting mechanisms 120, 128 are so switched by an output 110 from the second buffer 108 that the higher power supply voltage V
ddh or reduced power supply voltage V is selectively passed to the first buffer 104.
COPYRIGHT: (C)2005,JPO&NCIPI

Abstract translation: 要解决的问题：提供一种电平转换器，用于连接提供不同电源电压的两个电路，以及包含两个不同电压岛中的电平转换器接口电路的集成电路。 解决方案：用强制电源V向第一缓冲器104供电，第一缓冲器104从较低电压电路接收输入信号102。 第一缓冲器104驱动提供较高电源电压V SB3hh的第二缓冲器108。 电源选择机构120,128由来自第二缓冲器108的输出110进行切换，使得较高的电源电压V SB =或降低的电源电压V被选择性地传递到第一缓冲器104。 P>版权所有（C）2005，JPO＆NCIPI

公开(公告)号：SG160271A1

公开(公告)日：2010-04-29

申请号：SG2009048448

申请日：2009-07-17

Applicant: IBM

Inventor： XIANG HUA ,  ECONOMIKOS LAERTIS ,  FAYAZ MOHAMMED FAZIL ,  PURI RUCHIR ,  GRECO STEPHEN EDWARD ,  O NEIL PATRICIA A

Abstract: Methods, apparatus and computer program products provide a fast and accurate model for simulating the effects of chemical mechanical polishing (CMP) steps during fabrication of an integrated circuit by generating a design of an integrated circuit; while generating the design of the integrated circuit, using a simplified model to predict at least one physical characteristic of the integrated circuit which results from a CMP processing step to be used during manufacture of the integrated circuit, wherein the simplified model is derived from simulations performed prior to the design generation activities using a comprehensive simulation program used to model the physical characteristic; predicting performance of the integrated circuit using the predicted physical characteristic; and adjusting the design of the integrated circuit in dependence on the performance prediction.