公开(公告)号：WO2007063044A3

公开(公告)日：2007-11-08

申请号：PCT/EP2006068939

申请日：2006-11-27

Applicant: IBM ,  IBM UK ,  GRECO STEPHEN EDWARD ,  HEDBERG ERIK LEIGH ,  JUNG DAE-YOUNG ,  MCLAUGHLIN PAUL STEPHEN ,  MUZZY CHRISTOPHER DAVID ,  ROHRER NORMAN JAY ,  WYNNE JEAN ELIZABETH

Inventor： GRECO STEPHEN EDWARD ,  HEDBERG ERIK LEIGH ,  JUNG DAE-YOUNG ,  MCLAUGHLIN PAUL STEPHEN ,  MUZZY CHRISTOPHER DAVID ,  ROHRER NORMAN JAY ,  WYNNE JEAN ELIZABETH

IPC: H01L23/525

CPC classification number: H01L23/5258 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present invention relates to a laser fuse structure for high power applications. Specifically, the laser fuse structure of the present invention comprises first and second conductive supporting elements (12a, 12b) , at least one conductive fusible link (14) , first and second connection elements (20a, 20b) , and first and second metal lines (22a, 22b) . The conductive supporting elements (12a, 12b) , the conductive fusible link (14) , and the metal lines (22a, 22b) are located at a first metal level (3) , while the connect elements (20a, 20b) are located at a second, different metal level (4) and are connected to the conductive supporting elements (12a, 12b) and the metal lines (22a, 22b) by conductive via stacks (18a, 18b, 23a, 23b) that extend between the first and second metal levels (3, 4).

Abstract translation: 本发明涉及一种用于大功率应用的激光熔丝结构。 具体地，本发明的激光熔丝结构包括第一和第二导电支撑元件（12a，12b），至少一个导电熔丝（14），第一和第二连接元件（20a，20b）以及第一和第二金属线 （22a，22b）。 导电支撑元件（12a，12b），导电熔丝（14）和金属线（22a，22b）位于第一金属层（3）处，而连接元件（20a，20b）位于 第二不同的金属级（4），并且通过导电通孔叠层（18a，18b，23a，23b）与导电支撑元件（12a，12b）和金属线（22a，22b）连接， 第二金属含量（3,4）。

公开(公告)号：JPH10209071A

公开(公告)日：1998-08-07

申请号：JP154298

申请日：1998-01-07

Applicant: IBM

Inventor： GRECO NANCY ANNE ,  GRECO STEPHEN EDWARD ,  WAGNER TINA JANE

IPC: H01L21/28 ,  H01L21/768

Abstract: PROBLEM TO BE SOLVED: To obtain perfect optical resolution of holes and bars by using a conventional manufacturing equipment, by forming a plurality of second aperture parts which correspond to a plurality of second patterned features and stretch through a first and a second layers, in the second layer, filling the aperture parts. SOLUTION: A first layer is formed on a semiconductor substrate 4, and only a plurality of first features having a first feature size are patterned on the first layer. Parts of the first layer which correspond to the patterned first features are eliminated, and a plurality of aperture parts are formed in the first layer and filled. A second layer is formed on the first layer and the filled aperture parts, a plurality of second features having a second feature size are patterned on the second layer, and parts of the first and the second layer which correspond to the patterned second features are eliminated. As a result, a plurality of second aperture parts which correspond to a plurality of the second patterned features and stretch through the first and the second layers are formed in the second layer and filled.

公开(公告)号：JP2010079896A

公开(公告)日：2010-04-08

申请号：JP2009209893

申请日：2009-09-11

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： XIANG HUA ,  ECONOMIKOS LAERTIS ,  FAYAZ MOHAMMED FAZIL ,  GRECO STEPHEN EDWARD ,  O'NEIL PATRICIA A ,  PURI RUCHIR

IPC: G06F17/50 ,  H01L21/82

CPC classification number: G06F17/5009 ,  G06F2217/12 ,  Y02P90/265

Abstract: PROBLEM TO BE SOLVED: To provide a method, apparatus and computer program for performing simulation of influence of a manufacturing process to electrical performance in the integrated circuit during design stage.
SOLUTION: Methods, apparatus and computer program provide a fast and accurate model for simulating the effects of chemical mechanical polishing (CMP) steps during fabrication of an integrated circuit by generating a design of an integrated circuit, using a simplified model while generating the design of the integrated circuit, predicting at least one physical characteristic of the integrated circuit which results from a processing step to be used during manufacture of the integrated circuit, wherein the simplified model is derived from simulations performed prior to the design generation activities using a comprehensive simulation program used to model the physical characteristic; predicting performance of the integrated circuit using the predicted physical characteristic; and adjusting the design of the integrated circuit in dependence on the performance prediction.
COPYRIGHT: (C)2010,JPO&INPIT

Abstract translation: 要解决的问题：提供一种用于在设计阶段期间对集成电路中的制造过程对电气性能的影响进行模拟的方法，装置和计算机程序。 解决方案：方法，设备和计算机程序提供了一种快速准确的模型，用于在集成电路制造过程中模拟化学机械抛光（CMP）步骤的效果，通过使用简化模型生成集成电路的设计，同时产生 集成电路的设计，预测由在集成电路的制造期间使用的处理步骤产生的集成电路的至少一个物理特性，其中简化模型是从使用 综合仿真程序用于建模物理特性; 使用预测的物理特性预测集成电路的性能; 并根据性能预测调整集成电路的设计。 版权所有（C）2010，JPO＆INPIT

公开(公告)号：SG125963A1

公开(公告)日：2006-10-30

申请号：SG200403087

申请日：2001-12-11

Applicant: IBM

Inventor： DALTON TIMOTHY JOSEPH ,  GRECO STEPHEN EDWARD ,  HEDRICK JEFFREY CURTIS ,  NITTA SATYANARANA V ,  PURUSHOTHAMAN SAMPATH ,  RODBELL KENNETH PARKER ,  ROSENBERG ROBERT

IPC: H01L21/31 ,  H01L21/316 ,  H01L21/3205 ,  H01L21/768 ,  H01L23/532

Abstract: A method for forming a porous dielectric material layer (14) in an electronic structure (70) and the stricture (70) formed are disclosed. In the method, a porous dielectric layer (14) in a semiconductor device (70) can be formed by first forming (10) a non-porous dielectric layer (14),- then partially curing (20), patterning (30) by reactive ion etching, and final curing (40) the non-porous dielectric layer (14) at a higher temperature than the partial curing (20) temperature to transform the non-porous dielectric material (14) into a porous dielectric material (14), thus achieving 'a dielectric material that has significantly improved dielectric constant, i.e. smaller than 2.6. The non-porous dielectric material (14) may be formed by embedding a thermally stable dielectric material such as methyl silsesquioxane, hydrogen silsesquioxane, benzocyclobutene or aromatic thermoset polymers with a second phase polymeric material therein such that, at the higher curing temperature, the second phase polymeric material substantially volatilizes to leave voids behind forming a void-filled dielectric material.

公开(公告)号：DE68920291T2

公开(公告)日：1995-07-06

申请号：DE68920291

申请日：1989-10-10

Applicant: IBM

Inventor： GRECO NANCY ANN ,  GRECO STEPHEN EDWARD

IPC: H01L21/3213 ,  H01L21/3205 ,  H01L21/768 ,  H05K3/46 ,  H01L21/60 ,  G03F7/008

Abstract: A method is provided for forming a conductive stud and line over a surface (12), comprising the steps of forming at least a first layer of material (14) over the region on the surface whereat the conductive stud and line are to be formed; forming a layer (22) of dual image photoresist over the material; exposing the dual image photoresist to radiation so as to form at least first and second regions (22A, 22B, 22C) exhibiting different development characteristics; developing the first region (22A) so as to expose a portion of the material; removing the exposed portion of the material so as to define the position of one of the conductive line or stud; developing the second region to expose more of the material; and removing the newly exposed portion of material so as to define the position of the other of the conductive line (16 min /18 min ) or stud (20 min ).

公开(公告)号：SG160271A1

公开(公告)日：2010-04-29

申请号：SG2009048448

申请日：2009-07-17

Applicant: IBM

Inventor： XIANG HUA ,  ECONOMIKOS LAERTIS ,  FAYAZ MOHAMMED FAZIL ,  PURI RUCHIR ,  GRECO STEPHEN EDWARD ,  O NEIL PATRICIA A

Abstract: Methods, apparatus and computer program products provide a fast and accurate model for simulating the effects of chemical mechanical polishing (CMP) steps during fabrication of an integrated circuit by generating a design of an integrated circuit; while generating the design of the integrated circuit, using a simplified model to predict at least one physical characteristic of the integrated circuit which results from a CMP processing step to be used during manufacture of the integrated circuit, wherein the simplified model is derived from simulations performed prior to the design generation activities using a comprehensive simulation program used to model the physical characteristic; predicting performance of the integrated circuit using the predicted physical characteristic; and adjusting the design of the integrated circuit in dependence on the performance prediction.

公开(公告)号：HK1055641A1

公开(公告)日：2004-01-16

申请号：HK03107854

申请日：2003-10-31

Applicant: IBM

Inventor： DALTON TIMOTHY JOSEPH ,  GRECO STEPHEN EDWARD ,  HEDRICK JEFFREY CURTIS ,  NITTA SATYANARAYANA V ,  PURUSHOTHAMAN SAMPATH ,  RODBELL KENNETH PARKER ,  ROSENBERG ROBERT

IPC: H01L21/316 ,  H01L21/31 ,  H01L21/768 ,  H01L23/532 ,  H01L

Abstract: A method for forming a porous dielectric material layer in an electronic structure and the structure formed are disclosed. In the method, a porous dielectric layer in a semiconductor device can be formed by first forming a non-porous dielectric layer, then partially curing, patterning by reactive ion etching, and final curing the non-porous dielectric layer at a higher temperature than the partial curing temperature to transform the non-porous dielectric material into a porous dielectric material, thus forming a dielectric material that has a low dielectric constant, i.e. smaller than 2.6. The non-porous dielectric material may be formed by embedding a thermally stable dielectric material such as methyl silsesquioxane, hydrogen silsesquioxane, benzocyclobutene or aromatic thermoset polymers with a second phase polymeric material therein such that, at the higher curing temperature, the second phase polymeric material substantially volatilizes to leave voids behind forming a void-filled dielectric material.

公开(公告)号：DE3751127D1

公开(公告)日：1995-04-13

申请号：DE3751127

申请日：1987-04-28

Applicant: IBM

Inventor： GRECO STEPHEN EDWARD ,  LYONS CHRISTOPHER FRANCIS ,  YANG JER-MING

IPC: H01L21/30 ,  C08J9/26 ,  G03C1/00 ,  G03F7/004 ,  G03F7/26 ,  G03F7/30 ,  G03F7/38 ,  H01L21/027

公开(公告)号：DE68920291D1

公开(公告)日：1995-02-09

申请号：DE68920291

申请日：1989-10-10

Applicant: IBM

Inventor： GRECO NANCY ANN ,  GRECO STEPHEN EDWARD

IPC: H01L21/3213 ,  H01L21/3205 ,  H01L21/768 ,  H05K3/46 ,  H01L21/60 ,  G03F7/008

Abstract: A method is provided for forming a conductive stud and line over a surface (12), comprising the steps of forming at least a first layer of material (14) over the region on the surface whereat the conductive stud and line are to be formed; forming a layer (22) of dual image photoresist over the material; exposing the dual image photoresist to radiation so as to form at least first and second regions (22A, 22B, 22C) exhibiting different development characteristics; developing the first region (22A) so as to expose a portion of the material; removing the exposed portion of the material so as to define the position of one of the conductive line or stud; developing the second region to expose more of the material; and removing the newly exposed portion of material so as to define the position of the other of the conductive line (16 min /18 min ) or stud (20 min ).

公开(公告)号：DE3684504D1

公开(公告)日：1992-04-30

申请号：DE3684504

申请日：1986-04-11

Applicant: IBM

Inventor： GRECO STEPHEN EDWARD ,  GREEN DENNIS CLINTON

IPC: C08F12/00 ,  C08F12/34 ,  G03F7/023 ,  G03F7/028 ,  G03F7/038 ,  H01L21/027 ,  G03F7/021

Abstract: A film forming, radiation sensitive resist composition having improved thermal stability and a reduced dissolution rate in developer solutions, comprised of a sensitizer and a polyalkenyl phenol such as a polyvinyl phenol cross-linked, prior to irradiation, with a polyfunctional cross-linking agent such as dimethylol p-cresol or hexamethylene tetramine and a process for the production of a resist image using said composition is described.