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    VERTICAL TRANSISTOR TRENCH CAPACITOR DRAM CELL AND METHOD OF MAKING THE SAME
    4.
    发明申请
    VERTICAL TRANSISTOR TRENCH CAPACITOR DRAM CELL AND METHOD OF MAKING THE SAME 审中-公开
    垂直晶体管TRENCH电容器DRAM单元及其制造方法

    公开(公告)号：WO0229888A3

    公开(公告)日：2002-08-29

    申请号：PCT/US0127366

    申请日：2001-08-31

    Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

    Inventor： DYER THOMAS W ,  KNORR ANDREAS ,  ECONOMIKOS LAERTIS ,  HALLE SCOTT

    IPC: H01L21/8242 ,  H01L27/108

    CPC classification number: H01L27/10864 ,  H01L27/10891

    Abstract: A Top Oxide Method is used to form an oxide layer over an array of vertical transistors as in a trench dynamic random access memory (DRAM) array with vertically stacked access metal oxide semiconductor field effect transistors (MOSFETs). The Top Oxide is formed by first forming the vertical devices with the pad nitride (16) remaining in place. Once the devices have been formed and the gate polysilicon (18) has been planarized down to the surface of the pad nitride, the pad nitride is stripped away leaving the tops of the gate polysilicon plugs extending above the active silicon surface. This pattern of polysilicon plugs defines the pattern over which the Top Oxide is deposited. The deposited Top Oxide (21) fills the regions between and on top of the polysilicon plugs. The Top Oxide is than planarized back to the tops of the polysilicon plugs so contacts can be made between the passing interconnects and the gates of the vertical devices. The Top Oxide layer serves to separate the passing interconnects from the active silicon thereby reducing capacitive coupling between the two levels and providing a robust etch-stop layer for the reactive ion etch (RIE) patterning of the subsequent interconnect level.

    Abstract translation: 如在具有垂直堆叠的存取金属氧化物半导体场效应晶体管（MOSFET）的沟槽动态随机存取存储器（DRAM）阵列中，顶部氧化物方法用于在垂直晶体管阵列上形成氧化物层。 顶部氧化物通过首先形成具有衬垫氮化物（16）保持就位的垂直器件而形成。 一旦器件已经形成并且栅极多晶硅（18）已被平坦化到衬垫氮化物的表面，衬垫氮化物被剥离，留下栅极多晶硅插塞的顶部延伸到有源硅表面之上。 这种多晶硅插塞的图形定义了顶部氧化物沉积的图案。 沉积的顶部氧化物（21）填充多晶硅插塞之间和之上的区域。 顶部氧化物被平坦化回到多晶硅插塞的顶部，因此可以在通过的互连件和垂直装置的栅极之间形成接触。 顶部氧化物层用于将通过的互连与有源硅分离，从而减少两个电平之间的电容耦合，并提供用于后续互连电平的反应离子蚀刻（RIE）图案化的鲁棒蚀刻停止层。

    METHOD FOR POLISHING DIELECTRIC LAYERS USING FIXED ABRASIVE PADS
    5.
    发明申请
    METHOD FOR POLISHING DIELECTRIC LAYERS USING FIXED ABRASIVE PADS 审中-公开
    使用固定磨砂垫抛光电介质层的方法

    公开(公告)号：WO0249090A3

    公开(公告)日：2003-05-01

    申请号：PCT/US0144921

    申请日：2001-11-29

    Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

    Inventor： ECONOMIKOS LAERTIS ,  RAMACHANDRAN RAVIKUMAR ,  SIMPSON ALEXANDER

    IPC: H01L21/3105

    CPC classification number: H01L21/31053

    Abstract: A method for polishing a dielectric layer containing silicon (16) provides a fluorine-based compound (34) during a polishing process. The dielectric layer is polished in the presence of the fluorine based compound to accelerate a polishing rate of the dielectric layer.

    Abstract translation: 用于抛光含硅（16）的电介质层的方法在抛光过程中提供氟基化合物（34）。 在氟基化合物的存在下对电介质层进行研磨，以加速电介质层的研磨速度。

    Method of reducing stress within metallic cover of integrated circuit, and integrated circuit produced using the method
    7.
    发明专利
    Method of reducing stress within metallic cover of integrated circuit, and integrated circuit produced using the method 审中-公开
    集成电路金属外壳中应力减小的方法和使用该方法生产的集成电路

    公开(公告)号：JPH11274158A

    公开(公告)日：1999-10-08

    申请号：JP4899

    申请日：1999-01-04

    Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレイション

    Inventor： ARNDT KENNETH C ,  CONTI RICHARD A ,  DOBUZINSKY DAVID M ,  ECONOMIKOS LAERTIS ,  GAMBINO JEFFREY P ,  HOH PETER D ,  NARAYAN CHANDRASEKHAR

    IPC: H01L21/302 ,  H01L21/3065 ,  H01L21/3205 ,  H01L21/3213 ,  H01L21/768

    CPC classification number: H01L21/76804 ,  H01L21/32136 ,  H01L21/76835 ,  H01L21/76885

    Abstract: PROBLEM TO BE SOLVED: To check cracks within a final passivation laver 13 of an integrated circuit by reducing the stresses within a peripheral dielectric which are due to acute corner of a circuit pattern.
    SOLUTION: Stresses generally induced inside a dielectric is reduced by formings 15 and 17, at lower corner 14" of a circuit pattern 11 before adhering an outer layer (that is, a passivation layer) 13. When patterning it by metallic RIE process, this kind of rounding of the corner is achieved by a two-step metallic etching process, including the first step of creating a vertical sidewall and the second step of tapering the lower part of the vertical sidewall or creating a tapered spacer 15 along the under section of the vertical sidewall. When patterning it by a die machine process, this kind of rounding of the corner is achieved by a two-step trench etching process, including a first step of creating a vertical sidewall and a second step of creating a tapered side wall along the under section of the vertical sidewall.
    COPYRIGHT: (C)1999,JPO

    Abstract translation: 要解决的问题：通过减少外围电介质中由于电路图案的急剧拐角引起的应力来检查集成电路的最终钝化层13内的裂纹。 解决方案：在粘附外层（即钝化层）13之前的电路图案11的下角14“处，通过结构15和17减小电介质内部的应力。当通过金属RIE工艺对其进行图案化时， 通过两步金属蚀刻工艺实现角部的圆角化，包括形成垂直侧壁的第一步骤和使垂直侧壁的下部逐渐变细的第二步骤或者沿着垂直侧壁的下部形成锥形间隔件15 垂直侧壁，当通过模具机加工对其进行图案化时，通过两步沟槽蚀刻工艺实现角部圆化，包括形成垂直侧壁的第一步骤和产生锥形侧壁的第二步骤 沿着垂直侧壁的下部。

    Apparatus, method and computer program for fast simulation of manufacturing effect during integrated circuit design
    8.
    发明专利
    Apparatus, method and computer program for fast simulation of manufacturing effect during integrated circuit design 有权
    集成电路设计中制造效率快速模拟的装置，方法和计算机程序

    公开(公告)号：JP2010079896A

    公开(公告)日：2010-04-08

    申请号：JP2009209893

    申请日：2009-09-11

    Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

    Inventor： XIANG HUA ,  ECONOMIKOS LAERTIS ,  FAYAZ MOHAMMED FAZIL ,  GRECO STEPHEN EDWARD ,  O'NEIL PATRICIA A ,  PURI RUCHIR

    IPC: G06F17/50 ,  H01L21/82

    CPC classification number: G06F17/5009 ,  G06F2217/12 ,  Y02P90/265

    Abstract: PROBLEM TO BE SOLVED: To provide a method, apparatus and computer program for performing simulation of influence of a manufacturing process to electrical performance in the integrated circuit during design stage.
    SOLUTION: Methods, apparatus and computer program provide a fast and accurate model for simulating the effects of chemical mechanical polishing (CMP) steps during fabrication of an integrated circuit by generating a design of an integrated circuit, using a simplified model while generating the design of the integrated circuit, predicting at least one physical characteristic of the integrated circuit which results from a processing step to be used during manufacture of the integrated circuit, wherein the simplified model is derived from simulations performed prior to the design generation activities using a comprehensive simulation program used to model the physical characteristic; predicting performance of the integrated circuit using the predicted physical characteristic; and adjusting the design of the integrated circuit in dependence on the performance prediction.
    COPYRIGHT: (C)2010,JPO&INPIT

    Abstract translation: 要解决的问题：提供一种用于在设计阶段期间对集成电路中的制造过程对电气性能的影响进行模拟的方法，装置和计算机程序。 解决方案：方法，设备和计算机程序提供了一种快速准确的模型，用于在集成电路制造过程中模拟化学机械抛光（CMP）步骤的效果，通过使用简化模型生成集成电路的设计，同时产生 集成电路的设计，预测由在集成电路的制造期间使用的处理步骤产生的集成电路的至少一个物理特性，其中简化模型是从使用 综合仿真程序用于建模物理特性; 使用预测的物理特性预测集成电路的性能; 并根据性能预测调整集成电路的设计。 版权所有（C）2010，JPO＆INPIT

    CHEMICAL MECHANICAL POLISHING METHOD USING FIXED ABRASIVE AND ABRASIVE-CONTAINING AQUEOUS FLUID MEDIUM
    9.
    发明专利
    CHEMICAL MECHANICAL POLISHING METHOD USING FIXED ABRASIVE AND ABRASIVE-CONTAINING AQUEOUS FLUID MEDIUM 审中-公开

    公开(公告)号：JP2003100680A

    公开(公告)日：2003-04-04

    申请号：JP2002176781

    申请日：2002-06-18

    Applicant: IBM ,  INFINEON TECHNOLOGIES CORP

    Inventor： ECONOMIKOS LAERTIS ,  SIMPSON ALEXANDER

    IPC: B24B57/02 ,  B24B37/04 ,  C09K3/14 ,  H01L21/304 ,  H01L21/3105 ,  H01L21/76 ,  B24B37/00

    Abstract: PROBLEM TO BE SOLVED: To provide a chemical mechanical polishing method using fixed abrasive by which the thicknesses of oxide layers, particularly, siliceous oxide layers can be reduced quickly and effectively. SOLUTION: This chemical mechanical polishing method is characterized preferably by at least one step of simultaneously using a fixed-abrasive polishing member and an aqueous liquid medium containing an abrasive. When the first oxide layer to be polished has topographic variation, a topography reducing step using the fixed abrasive and an aqueous liquid medium containing a polyelectrolyte may be performed as part of the polishing method, including the reduction of the topography variation (height difference) extended to the oxide layer provided on a substrate before performing this thickness reducing method.

    STRUCTURE OF SEMICONDUCTOR FOR REDUCING CONTACT RESISTANCE AND FORMATION METHOD THEREFOR
    10.
    发明专利
    STRUCTURE OF SEMICONDUCTOR FOR REDUCING CONTACT RESISTANCE AND FORMATION METHOD THEREFOR 失效

    公开(公告)号：JP2000331954A

    公开(公告)日：2000-11-30

    申请号：JP2000131647

    申请日：2000-04-28

    Applicant: IBM

    Inventor： ECONOMIKOS LAERTIS ,  JONATHAN FORUTAMIRAA ,  BIYONGYU PAAKU

    IPC: H01L21/28 ,  H01L21/225 ,  H01L21/285 ,  H01L21/336 ,  H01L21/768 ,  H01L23/522 ,  H01L29/786

    Abstract: PROBLEM TO BE SOLVED: To reduce contact resistance by containing a contact material layer and a dopant layer obtained from amorphous silicon in a contact material in contact with an epitaxial single-crystal silicon substrate and setting the concentration within a specific thickness range from the substrate to a specific, average dopant concentration. SOLUTION: A region, with a thickness of approximately 500 Å of a contact material in contact with an epitaxial single-crystal silicon substrate, is obtained from amorphous silicon with an average dopant concentration of at least 1020 dopant atom per cm3. A part with approximately 500 Å of a contact point includes the layer of a material, obtained from the non-doped amorphous silicon which is arranged alternately with the doping layer. Such a doping layer is separated by a layer obtained from the non-doped amorphous silicon, thus reducing the contact resistance.

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