公开(公告)号：GB2606885A

公开(公告)日：2022-11-23

申请号：GB202208932

申请日：2020-10-26

Applicant: IBM

Inventor： NIKOLAOS PAPANDREOU ,  ROMAN PLETKA ,  RADU STOICA ,  NIKOLAS IOANNOU ,  SASA TOMIC ,  CHARALAMPOS POZIDIS

IPC: G06F12/00 ,  G11C11/56

Abstract: A method, computer program product, and system for controlling operation of an array of non-volatile memory cells comprising cells which are selectively configurable for single-bit and multibit storage. The method includes a memory controller selectively configuring the array for operation in a hybrid mode, in which the array comprises both cells configured for single-bit storage and cells configured for multibit storage, and a multibit mode in which all cells in the array are configured for multibit storage. The method further includes the memory controller dynamically switching between the hybrid and multibit mode configurations of the array corresponding to array capacity-usage traversing a defined threshold level associated with enhance endurance of the array.

公开(公告)号：GB2606885B

公开(公告)日：2023-10-11

申请号：GB202208932

申请日：2020-10-26

Applicant: IBM

Inventor： NIKOLAOS PAPANDREOU ,  ROMAN PLETKA ,  RADU STOICA ,  NIKOLAS IOANNOU ,  SASA TOMIC ,  CHARALAMPOS POZIDIS

IPC: G06F12/00 ,  G11C11/56

Abstract: Aspects of the present invention disclose a method, computer program product, and system for controlling operation of an array of non-volatile memory cells comprising cells which are selectively configurable for single-bit and multibit storage. The method includes a memory controller selectively configuring the array for operation in a hybrid mode, in which the array comprises both cells configured for single-bit storage and cells configured for multibit storage, and a multibit mode in which all cells in the array are configured for multibit storage. The method further includes the memory controller dynamically switching between the hybrid and multibit mode configurations of the array corresponding to array capacity-usage traversing a defined threshold level associated with enhance endurance of the array.

公开(公告)号：GB2604517A

公开(公告)日：2022-09-07

申请号：GB202207336

申请日：2020-10-16

Applicant: IBM

Inventor： NIKOLAOS PAPANDREOU ,  CHARALAMPOS POZIDIS ,  NIKOLAS IOANNOU ,  ROMAN PLETKA ,  RADU STOICA ,  SASA TOMIC ,  AARON FRY ,  TIMOTHY FISHER

IPC: G06F11/07 ,  G06F11/10 ,  G11C16/26

Abstract: A computer-implemented method, according to one approach, includes: using a first calibration scheme to calibrate the given page in the block by calculating a first number of independent read voltage offset values for the given page (606). An attempt is made to read the calibrated given page (608), and in response to determining that an error correction code failure occurred when attempting to read the calibrated given page, a second calibration scheme is used to recalibrate the given page in the block (612). The second calibration scheme is configured to calculate a second number of independent read voltage offset values for the given page. An attempt to read the recalibrated given page is also made (614). In response to determining that an error correction code failure did occur when attempting to read the recalibrated given page, one or more instructions to relocate data stored in the given page are sent (618).