公开(公告)号：GB2606885A

公开(公告)日：2022-11-23

申请号：GB202208932

申请日：2020-10-26

Applicant: IBM

Inventor： NIKOLAOS PAPANDREOU ,  ROMAN PLETKA ,  RADU STOICA ,  NIKOLAS IOANNOU ,  SASA TOMIC ,  CHARALAMPOS POZIDIS

IPC: G06F12/00 ,  G11C11/56

Abstract: A method, computer program product, and system for controlling operation of an array of non-volatile memory cells comprising cells which are selectively configurable for single-bit and multibit storage. The method includes a memory controller selectively configuring the array for operation in a hybrid mode, in which the array comprises both cells configured for single-bit storage and cells configured for multibit storage, and a multibit mode in which all cells in the array are configured for multibit storage. The method further includes the memory controller dynamically switching between the hybrid and multibit mode configurations of the array corresponding to array capacity-usage traversing a defined threshold level associated with enhance endurance of the array.

公开(公告)号：GB2598878B

公开(公告)日：2022-08-03

申请号：GB202200305

申请日：2020-06-23

Applicant: IBM

Inventor： ROMAN A PLETKA ,  RADU IOAN STOICA ,  SASA TOMIC ,  NIKOLAOS PAPANDREOU ,  NIKOLAS IOANNOU ,  AARON DANIEL FRY ,  TIMOTHY FISHER ,  CHARALAMPOS POZIDIS ,  ANDREW WALLS

IPC: G06F3/06

Abstract: A computer-implemented method, according to one embodiment, includes: determining whether a number of blocks included in a first ready-to-use (RTU) queue is in a first range of the first RTU queue. In response to determining that the number of blocks included in the first RTU queue is in the first range, a determination is made as to whether a number of blocks included in a second RTU queue is in a second range of the second RTU queue. Moreover, in response to determining that the number of blocks included in the second RTU queue is not in the second range, valid data is relocated from one of the blocks in a first pool which corresponds to the first RTU queue. The block in the first pool is erased, and transferred from the first pool to the second RTU queue which corresponds to a second pool.

公开(公告)号：GB2599061B

公开(公告)日：2022-07-27

申请号：GB202200312

申请日：2020-06-23

Applicant: IBM

Inventor： ROMAN ALEXANDER PLETKA ,  AARON DANIEL FRY ,  TIMOTHY FISHER ,  SASA TOMIC ,  NIKOLAOS PAPANDREOU ,  NIKOLAS IOANNOU ,  RADU IOAN STOICA ,  CHARALAMPOS POZIDIS ,  ANDREW WALLS

IPC: G06F3/06

Abstract: A computer-implemented method, according to one embodiment, includes: maintaining a block switching metric for each block of memory in the storage system. A determination is made as to whether a first block in a first pool should be transferred to a second pool according to a block switching metric which corresponds to the first block. In response to determining that the first block in the first pool should be transferred to the second pool according to the block switching metric which corresponds to the first block, the first block is erased. The first block is then transferred from the first pool to a second RTU queue which corresponds to the second pool. A second block in the second pool is also erased and transferred from the second pool to a first RTU queue which corresponds to the first pool.

公开(公告)号：GB2556577A

公开(公告)日：2018-05-30

申请号：GB201801788

申请日：2016-12-09

Applicant: IBM

Inventor： ROMAN PLETKA ,  CHARLES JOHN CAMP ,  AARON DANIEL FRY ,  TIMOTHY JOHN FISHER ,  NIKOLAS IOANNOU ,  SASA TOMIC ,  THOMAS PARNELL

IPC: G06F3/06 ,  G06F12/02 ,  G06F11/10

Abstract: A data storage system includes a controller and a non-volatile memory array having a plurality of blocks each including a plurality of physical pages. The controller maintains a logical-to-physical translation (LPT)data structure that maps logical addresses to physical addresses and implements a first data protection scheme that stripes write data over the plurality of physica1 blocks. In response to a read request requesting data from a target page stripe, the controller detecting errors in multiple physical pages of the target page stripe. In responsive to detecting errors in multiple physical pages of the target page stripe, the controller scans the LPT data structure to identify a set of logical addresses mapped to the target page stripe and triggers recovery of the target page stripe by a higher level controller that implements a second data protection scheme, wherein triggering recovery includes transmitting the set of logical addresses to the higher level controller.

公开(公告)号：GB2600310A

公开(公告)日：2022-04-27

申请号：GB202200757

申请日：2020-06-25

Applicant: IBM

Inventor： ROMAN ALEXANDER PLETKA ,  TIMOTHY FISHER ,  AARON DANIEL FRY ,  NIKOLAOS PAPANDREOU ,  NIKOLAS IOANNOU ,  SASA TOMIC ,  RADU IOAN STOICA ,  CHARALAMPOS POZIDIS ,  ANDREW WALLS

IPC: G06F3/06

Abstract: A computer-implemented method, according to one approach, includes: receiving write requests, accumulating the write requests in a destage buffer, and determining a current read heat value of each logical page which corresponds to the write requests. Each of the write requests is assigned to a respective write queue based on the current read heat value of each logical page which corresponds to the write requests. Moreover, each of the write queues correspond to a different page stripe which includes physical pages, the physical pages included in each of the respective page stripes being of a same type. Furthermore, data in the write requests is destaged from the write queues to their respective page stripes. Other systems, methods, and computer program products are described in additional approaches.

公开(公告)号：GB2599529A

公开(公告)日：2022-04-06

申请号：GB202117864

申请日：2020-05-28

Applicant: IBM

Inventor： SASA TOMIC ,  ROMAN ALEXANDER PLETKA ,  NIKOLAS IOANNOU ,  NIKOLAOS PAPANDREOU ,  AARON DANIEL FRY ,  TIMOTHY FISHER ,  RADU IOAN STOICA

IPC: G06F3/06

Abstract: A non-volatile memory includes a plurality of physical blocks of storage each including a respective plurality of cells, where each of the plurality of cells is individually capable of storing multiple bits of data. A controller assigns physical blocks among the plurality of physical blocks to a first pool containing physical blocks operating in a first (e.g., QLC) mode for storing a greater number of bits per cell and assigns other physical blocks among the plurality of physical blocks to a second pool containing physical blocks operating in a second (e.g., SLC) mode for storing a lesser number of bits per cell. The controller transfers physical blocks between the first pool and the second pool based on at least bit error rates measured for the transferred physical blocks.

公开(公告)号：GB2606885B

公开(公告)日：2023-10-11

申请号：GB202208932

申请日：2020-10-26

Applicant: IBM

Inventor： NIKOLAOS PAPANDREOU ,  ROMAN PLETKA ,  RADU STOICA ,  NIKOLAS IOANNOU ,  SASA TOMIC ,  CHARALAMPOS POZIDIS

IPC: G06F12/00 ,  G11C11/56

Abstract: Aspects of the present invention disclose a method, computer program product, and system for controlling operation of an array of non-volatile memory cells comprising cells which are selectively configurable for single-bit and multibit storage. The method includes a memory controller selectively configuring the array for operation in a hybrid mode, in which the array comprises both cells configured for single-bit storage and cells configured for multibit storage, and a multibit mode in which all cells in the array are configured for multibit storage. The method further includes the memory controller dynamically switching between the hybrid and multibit mode configurations of the array corresponding to array capacity-usage traversing a defined threshold level associated with enhance endurance of the array.

公开(公告)号：GB2598878A

公开(公告)日：2022-03-16

申请号：GB202200305

申请日：2020-06-23

Applicant: IBM

Inventor： ROMAN A PLETKA ,  RADU IOAN STOICA ,  SASA TOMIC ,  NIKOLAOS PAPANDREOU ,  NIKOLAS IOANNOU ,  AARON DANIEL FRY ,  TIMOTHY FISHER ,  CHARALAMPOS POZIDIS ,  ANDREW WALLS

IPC: G06F3/06

Abstract: A computer-implemented method, according to one embodiment, includes: determining whether a number of blocks included in a first ready-to-use (RTU) queue is in a first range of the first RTU queue. In response to determining that the number of blocks included in the first RTU queue is in the first range, a determination is made as to whether a number of blocks included in a second RTU queue is in a second range of the second RTU queue. Moreover, in response to determining that the number of blocks included in the second RTU queue is not in the second range, valid data is relocated from one of the blocks in a first pool which corresponds to the first RTU queue. The block in the first pool is erased, and transferred from the first pool to the second RTU queue which corresponds to a second pool.

公开(公告)号：GB2569060A

公开(公告)日：2019-06-05

申请号：GB201903697

申请日：2017-07-21

Applicant: IBM

Inventor： NIKOLAS IOANNOU ,  ROMAN PLETKA ,  CHENG-CHUNG SONG ,  RADU IOAN STOICA ,  SASA TOMIC ,  ANDREW DALE WALLS

IPC: G06F16/215

Abstract: A controller of a data storage system generates fingerprints of data blocks written to the data storage system. The controller maintains, in a data structure, respective state information for each of a plurality of data blocks. The state information for each data block can be independently set to indicate any of a plurality of states, including at least one deduplication state and at least one non-deduplication state. At allocation of a data block, the controller initializes the state information for the data block to a non-deduplication state and, thereafter, in response to detection of a write of duplicate of the data block to the data storage system, transitions the state information for the data block to a deduplication state. The controller selectively performs data deduplication for data blocks written to the data storage system based on the state information in the data structure and by reference to the fingerprints.

公开(公告)号：GB2556577B

公开(公告)日：2019-01-09

申请号：GB201801788

申请日：2016-12-09

Applicant: IBM

Inventor： ROMAN PLETKA ,  CHARLES JOHN CAMP ,  AARON DANIEL FRY ,  TIMOTHY JOHN FISHER ,  NIKOLAS IOANNOU ,  SASA TOMIC ,  THOMAS PARNELL

IPC: G06F12/02 ,  G06F3/06 ,  G06F11/10

Abstract: A data storage system includes a controller and a non-volatile memory array having a plurality of blocks each including a plurality of physical pages. The controller maintains a logical-to-physical translation (LPT) data structure that maps logical addresses to physical addresses and implements a first data protection scheme that stripes write data over the plurality of physical blocks. In response to a read request requesting data from a target page stripe, the controller detecting errors in multiple physical pages of the target page stripe. In responsive to detecting errors in multiple physical pages of the target page stripe, the controller scans the LPT data structure to identify a set of logical addresses mapped to the target page stripe and triggers recovery of the target page stripe by a higher level controller that implements a second data protection scheme, wherein triggering recovery includes transmitting the set of logical addresses to the higher level controller.