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公开(公告)号：GB2606885A
公开(公告)日：2022-11-23
申请号：GB202208932
申请日：2020-10-26
Applicant: IBM
Inventor： NIKOLAOS PAPANDREOU , ROMAN PLETKA , RADU STOICA , NIKOLAS IOANNOU , SASA TOMIC , CHARALAMPOS POZIDIS
Abstract: A method, computer program product, and system for controlling operation of an array of non-volatile memory cells comprising cells which are selectively configurable for single-bit and multibit storage. The method includes a memory controller selectively configuring the array for operation in a hybrid mode, in which the array comprises both cells configured for single-bit storage and cells configured for multibit storage, and a multibit mode in which all cells in the array are configured for multibit storage. The method further includes the memory controller dynamically switching between the hybrid and multibit mode configurations of the array corresponding to array capacity-usage traversing a defined threshold level associated with enhance endurance of the array.
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公开(公告)号：GB2513741B
公开(公告)日：2016-11-02
申请号：GB201409211
申请日：2012-10-19
Applicant: IBM
Inventor： LOKESH MOHAN GUPTA , EVANGELOS STRAVROS ELEFTHERIOU , IOANNIS KOLTSIDAS , XIAO-YU HU , ROMAN PLETKA , ROBERT HAAS , STEPHEN BLINICK , MICHAEL THOMAS BENHASE
IPC: G06F12/0888 , G06F12/0866 , G06F12/0897
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公开(公告)号：GB2604517A
公开(公告)日：2022-09-07
申请号：GB202207336
申请日：2020-10-16
Applicant: IBM
Inventor： NIKOLAOS PAPANDREOU , CHARALAMPOS POZIDIS , NIKOLAS IOANNOU , ROMAN PLETKA , RADU STOICA , SASA TOMIC , AARON FRY , TIMOTHY FISHER
Abstract: A computer-implemented method, according to one approach, includes: using a first calibration scheme to calibrate the given page in the block by calculating a first number of independent read voltage offset values for the given page (606). An attempt is made to read the calibrated given page (608), and in response to determining that an error correction code failure occurred when attempting to read the calibrated given page, a second calibration scheme is used to recalibrate the given page in the block (612). The second calibration scheme is configured to calculate a second number of independent read voltage offset values for the given page. An attempt to read the recalibrated given page is also made (614). In response to determining that an error correction code failure did occur when attempting to read the recalibrated given page, one or more instructions to relocate data stored in the given page are sent (618).
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公开(公告)号：GB2569060B
公开(公告)日：2019-11-13
申请号：GB201903697
申请日：2017-07-21
Applicant: IBM
Inventor： NIKOLAS IOANNOU , ROMAN PLETKA , CHENG-CHUNG SONG , RADU IOAN STOICA , SASA TOMIC , ANDREW DALE WALLS
IPC: G06F16/215
Abstract: A controller of a data storage system generates fingerprints of data blocks written to the data storage system. The controller maintains, in a data structure, respective state information for each of a plurality of data blocks. The state information for each data block can be independently set to indicate any of a plurality of states, including at least one deduplication state and at least one non-deduplication state. At allocation of a data block, the controller initializes the state information for the data block to a non-deduplication state and, thereafter, in response to detection of a write of duplicate of the data block to the data storage system, transitions the state information for the data block to a deduplication state. The controller selectively performs data deduplication for data blocks written to the data storage system based on the state information in the data structure and by reference to the fingerprints.
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Patent Agency Ranking
公开(公告)号：GB2606885B
公开(公告)日：2023-10-11
申请号：GB202208932
申请日：2020-10-26
Applicant: IBM
Inventor： NIKOLAOS PAPANDREOU , ROMAN PLETKA , RADU STOICA , NIKOLAS IOANNOU , SASA TOMIC , CHARALAMPOS POZIDIS
Abstract: Aspects of the present invention disclose a method, computer program product, and system for controlling operation of an array of non-volatile memory cells comprising cells which are selectively configurable for single-bit and multibit storage. The method includes a memory controller selectively configuring the array for operation in a hybrid mode, in which the array comprises both cells configured for single-bit storage and cells configured for multibit storage, and a multibit mode in which all cells in the array are configured for multibit storage. The method further includes the memory controller dynamically switching between the hybrid and multibit mode configurations of the array corresponding to array capacity-usage traversing a defined threshold level associated with enhance endurance of the array.
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公开(公告)号：GB2569060A
公开(公告)日：2019-06-05
申请号：GB201903697
申请日：2017-07-21
Applicant: IBM
Inventor： NIKOLAS IOANNOU , ROMAN PLETKA , CHENG-CHUNG SONG , RADU IOAN STOICA , SASA TOMIC , ANDREW DALE WALLS
IPC: G06F16/215
Abstract: A controller of a data storage system generates fingerprints of data blocks written to the data storage system. The controller maintains, in a data structure, respective state information for each of a plurality of data blocks. The state information for each data block can be independently set to indicate any of a plurality of states, including at least one deduplication state and at least one non-deduplication state. At allocation of a data block, the controller initializes the state information for the data block to a non-deduplication state and, thereafter, in response to detection of a write of duplicate of the data block to the data storage system, transitions the state information for the data block to a deduplication state. The controller selectively performs data deduplication for data blocks written to the data storage system based on the state information in the data structure and by reference to the fingerprints.
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公开(公告)号：GB2556577B
公开(公告)日：2019-01-09
申请号：GB201801788
申请日：2016-12-09
Applicant: IBM
Inventor： ROMAN PLETKA , CHARLES JOHN CAMP , AARON DANIEL FRY , TIMOTHY JOHN FISHER , NIKOLAS IOANNOU , SASA TOMIC , THOMAS PARNELL
Abstract: A data storage system includes a controller and a non-volatile memory array having a plurality of blocks each including a plurality of physical pages. The controller maintains a logical-to-physical translation (LPT) data structure that maps logical addresses to physical addresses and implements a first data protection scheme that stripes write data over the plurality of physical blocks. In response to a read request requesting data from a target page stripe, the controller detecting errors in multiple physical pages of the target page stripe. In responsive to detecting errors in multiple physical pages of the target page stripe, the controller scans the LPT data structure to identify a set of logical addresses mapped to the target page stripe and triggers recovery of the target page stripe by a higher level controller that implements a second data protection scheme, wherein triggering recovery includes transmitting the set of logical addresses to the higher level controller.
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公开(公告)号：GB2556577A
公开(公告)日：2018-05-30
申请号：GB201801788
申请日：2016-12-09
Applicant: IBM
Inventor： ROMAN PLETKA , CHARLES JOHN CAMP , AARON DANIEL FRY , TIMOTHY JOHN FISHER , NIKOLAS IOANNOU , SASA TOMIC , THOMAS PARNELL
Abstract: A data storage system includes a controller and a non-volatile memory array having a plurality of blocks each including a plurality of physical pages. The controller maintains a logical-to-physical translation (LPT)data structure that maps logical addresses to physical addresses and implements a first data protection scheme that stripes write data over the plurality of physica1 blocks. In response to a read request requesting data from a target page stripe, the controller detecting errors in multiple physical pages of the target page stripe. In responsive to detecting errors in multiple physical pages of the target page stripe, the controller scans the LPT data structure to identify a set of logical addresses mapped to the target page stripe and triggers recovery of the target page stripe by a higher level controller that implements a second data protection scheme, wherein triggering recovery includes transmitting the set of logical addresses to the higher level controller.
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公开(公告)号：GB2490412B
公开(公告)日：2017-12-13
申请号：GB201207226
申请日：2011-01-07
Applicant: IBM
Inventor： ROMAN PLETKA , EVANGELOS ELEFTHERIOU , ROBERT HAAS , XIAO-YU HU , YU-CHENG HSU , LOKESH MOHAN GUPTA , JOSEPH SMITH HYDE II , MICHAEL THOMAS BENHASE , ALFRED EMILIO SANCHEZ , KEVIN JOHN ASH
IPC: G06F12/0866
Abstract: An I/O enclosure module is provided with one or more I/O enclosures having a plurality of slots for receiving electronic devices. A host adapter is connected a first slot of the I/O enclosure module and is configured to connect a host to the I/O enclosure. A device adapter is connected to a second slot of the I/O enclosure module and is configured to connect a storage device to the I/O enclosure module. A flash cache is connected to a third slot of the I/O enclosure module and includes a flash-based memory configured to cache data associated with data requests handled through the I/O enclosure module. A primary processor complex manages data requests handled through the I/O enclosure module by communicating with the host adapter, device adapter, and flash cache to manage to the data requests.
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