公开(公告)号：US3622315A

公开(公告)日：1971-11-23

申请号：US3622315D

申请日：1968-11-14

Applicant: IBM

Inventor： BROOKMAN JOHN W ,  MURPHY JOHN B ,  REYNOLDS ZACK D

IPC: H01J31/38 ,  H04R23/00 ,  G03G ,  H01J31/48 ,  H04N5/76

CPC classification number: H04R23/006 ,  H01J31/38

Abstract: A photoerasable scan converter is described for converting digital and/or optical input to a raster signal output for storage in a buffer and subsequent monitoring. In combined image mode, a charge pattern representing a first image is painted on the photoconductive target of a Vidicon tube by an electron beam in directed-beam mode. A modification or modulation of a charge pattern representing a second image is provided on the target by exposing said screen to the second image through an optical system. The combined images, or charge patterns, are read out by electron beam scanning in raster mode. Any remanent charge on the target is erased by discharging with a short, high intensity flash of light. Similarly, a single image from either optical exposure or electron beam painting may be read out and erased.

公开(公告)号：US3476973A

公开(公告)日：1969-11-04

申请号：US3476973D

申请日：1968-01-15

Applicant: IBM

Inventor： CHESAREK DONALD J ,  REYNOLDS ZACK D

IPC: G09G1/10 ,  H01J29/70

CPC classification number: G09G1/10

公开(公告)号：CA878152A

公开(公告)日：1971-08-10

申请号：CA878152D

Applicant: IBM

Inventor： MARTIN HAROLD F ,  BROWN CAROLL J ,  CHESAREK DONALD J ,  FISK DALE E ,  REYNOLDS ZACK D ,  MA JOSEPH T

公开(公告)号：CA890091A

公开(公告)日：1972-01-04

申请号：CA890091D

Applicant: IBM

Inventor： CHESAREK DONALD J ,  REYNOLDS ZACK D

公开(公告)号：CA1035451A

公开(公告)日：1978-07-25

申请号：CA223596

申请日：1975-03-27

Applicant: IBM

Inventor： FISK DALE E ,  HOMAN MERLE E ,  MEILEY CHARLES L ,  REYNOLDS ZACK D ,  WATKINS ROBERT V ,  WIEDMER FRITZ S

IPC: H04Q3/52 ,  H04Q11/04

Abstract: A multiple of telephone or like communications signal transmission lines are interconnected in time division multiplex (TDM) mode by integrated semiconductor switching circuitry. Preferably, electronic solid state structure most suitable for embodying field effect transistors (FET) and like associated devices is arranged in modular chip components permitting extension to large numbers of transmission lines, as desired. Input or calling transmission line terminals are connected to node busses by FET switches in predetermined time sequence under control of a central processing unit. Preferably, a separate timing pulse train generating circuit is used for the switching operation. Output or called transmission line terminals are connected to the node busses in predetermined time sequence at which every calling line is sampled at least once each switching cycle. Signal bandwidth is adjustable by arranging the switching circuitry to sample a calling line one, two, or more times in each switching cycle. Conventional semiconductor structure inherently forms capacitors of substantial reactance between the node busses and points of reference potential. Circuitry is incorporated in the arrangement for discharging the capacitors prior to connecting the input signal lines to the node busses. The circuitry also incorporates FET switch elements arranged for isolating uncalled output terminals from the switching circuitry, and for short circuiting each pair of idle output terminals.