公开(公告)号：US3665103A

公开(公告)日：1972-05-23

申请号：US3665103D

申请日：1969-12-16

Applicant: IBM

Inventor： WATKINS ROBERT V

IPC: H04L27/10 ,  H04L27/12

CPC classification number: H04L27/10

Abstract: A data transmission system in which data to be transmitted is encoded using double frequency coding, the keying signal which defines the individual bit cells being in-phase with first and second carrier signals having frequencies equal to that of the keying signal frequency and twice that of the keying signal frequency. Opposite binary characterizations (''''zeros'''' and ''''ones'''') are respectively transmitted as a half-cycle of the first carrier signal or a full cycle of the second carrier signal within the appropriate bit cells, the synchronous relationship between the keying and carrier signals providing for bit cells of equal size and self-clocking. Encoded data is processed at the transmitting and receiving ends of a transmission line by circuitry which is transformer coupled to the line at both ends to provide isolation and minimize common mode noise and ground shift problems, and which is impedance matched to the line to provide high noise immunity.

公开(公告)号：CA1035451A

公开(公告)日：1978-07-25

申请号：CA223596

申请日：1975-03-27

Applicant: IBM

Inventor： FISK DALE E ,  HOMAN MERLE E ,  MEILEY CHARLES L ,  REYNOLDS ZACK D ,  WATKINS ROBERT V ,  WIEDMER FRITZ S

IPC: H04Q3/52 ,  H04Q11/04

Abstract: A multiple of telephone or like communications signal transmission lines are interconnected in time division multiplex (TDM) mode by integrated semiconductor switching circuitry. Preferably, electronic solid state structure most suitable for embodying field effect transistors (FET) and like associated devices is arranged in modular chip components permitting extension to large numbers of transmission lines, as desired. Input or calling transmission line terminals are connected to node busses by FET switches in predetermined time sequence under control of a central processing unit. Preferably, a separate timing pulse train generating circuit is used for the switching operation. Output or called transmission line terminals are connected to the node busses in predetermined time sequence at which every calling line is sampled at least once each switching cycle. Signal bandwidth is adjustable by arranging the switching circuitry to sample a calling line one, two, or more times in each switching cycle. Conventional semiconductor structure inherently forms capacitors of substantial reactance between the node busses and points of reference potential. Circuitry is incorporated in the arrangement for discharging the capacitors prior to connecting the input signal lines to the node busses. The circuitry also incorporates FET switch elements arranged for isolating uncalled output terminals from the switching circuitry, and for short circuiting each pair of idle output terminals.